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SN74HC573ADBR データシート(PDF) 2 Page - Texas Instruments

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部品番号 SN74HC573ADBR
部品情報  OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
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SN74HC573ADBR データシート(HTML) 2 Page - Texas Instruments

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SN54HC573A, SN74HC573A
OCTAL TRANSPARENT DTYPE LATCHES
WITH 3STATE OUTPUTS
SCLS147E − DECEMBER 1982 − REVISED SEPTEMBER 2003
2
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
OE
LE
D
OUTPUT
Q
L
H
H
H
L
HL
L
L
LX
Q0
H
X
X
Z
logic diagram (positive logic)
OE
LE
1D
1Q
1
11
2
19
To Seven Other Channels
C1
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC
−0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1)
±20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1)
±20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC)
±35 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND
±70 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 2): DB package
70
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package
58
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package
69
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package
83
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
−65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.


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