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SM65MLVD080DGGR データシート(PDF) 5 Page - Texas Instruments |
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SM65MLVD080DGGR データシート(HTML) 5 Page - Texas Instruments |
5 / 28 page www.ti.com DRIVER SWITCHING CHARACTERISTICS SN65MLVD080 SN65MLVD082 SLLS581B – SEPTEMBER 2003 – REVISED SEPTEMBER 2005 over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tpLH Propagation delay time, low-to-high-level output 1 1.5 2.4 ns tpHL Propagation delay time, high-to-low-level output 1 1.5 2.4 ns tr Differential output signal rise time 1 2 ns tf Differential output signal fall time See Figure 5 1 2 ns tsk(o) Output skew 350 ps tsk(p) Pulse skew (|tPHL– tPLH|) 0 150 ps tsk(pp) Part-to-part skew (2) 600 ps tjit(per) Period jitter, rms (1 standard deviation)(3) 4 ps 100 MHz clock input(4) tjit(c-c) Cycle-to-cycle jitter, rms 45 ps tjit(det) Deterministic jitter 150 ps 200 Mbps 215–1 PRBS input(5) tjit(pp) Peak-to-peak jitter(2)(6) 190 ps tPZH Enable time, high-impedance-to-high-level output 7 ns tPZL Enable time, high-impedance-to-low-level output 7 ns See Figure 6 tPHZ Disable time, high-level-to-high-impedance output 7 ns tPLZ Disable time, low-level-to-high-impedance output 7 ns (1) All typical values are at 25°C and with a 3.3-V supply voltage. (2) tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. (3) Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. (4) tr = tf = 0.5 ns (10% to 90%), measured over 30 k samples. (5) tr = tf = 0.5 ns (10% to 90%), measured over 100 k samples. (6) Peak-to-peak jitter includes jitter due to pulse skew (tsk(p)). 5 Submit Documentation Feedback |
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同様の説明 - SM65MLVD080DGGR |
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