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74ABT5074D データシート(PDF) 3 Page - NXP Semiconductors |
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74ABT5074D データシート(HTML) 3 Page - NXP Semiconductors |
3 / 13 page Philips Semiconductors Product data 74ABT5074 Synchronizing dual D-type flip-flop with metastable immune characteristics 2002 Dec 17 3 LOGIC SYMBOL Q0 Q0 Q1 Q1 56 98 VCC = Pin 14 GND = Pin 7 3 4 1 11 10 13 CP0 SD0 RD0 CP1 SD1 RD1 D0 D1 212 SA00002 IEC/IEEE SYMBOL 4 3 2 1 10 11 12 13 5 6 9 8 S S C1 C2 R 1D 2D R SA00003 LOGIC DIAGRAM VCC = Pin 14 GND = Pin 7 5, 9 6, 8 Q Q 4, 10 1, 13 3, 11 2, 12 SD RD CP D SF00048 FUNCTION TABLE INPUTS OUTPUTS OPERATING SD RD CP D Q Q MODE L H X X H L Asynchronous set H L X X L H Asynchronous reset L L X X L H Undetermined* H H ↑ h H L Load “1” H H ↑ l L H Load “0” H H ↑ X NC NC Hold NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to LOW-to-HIGH clock transition L = LOW voltage level l = LOW voltage level one set-up time prior to LOW-to-HIGH clock transition NC= No change from the previous set-up X = Don’t care ↑ = LOW-to-HIGH clock transition ↑ = Not LOW-to-HIGH clock transition * = This set-up is unstable and will change when either set or reset return to the HIGH level |
同様の部品番号 - 74ABT5074D |
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同様の説明 - 74ABT5074D |
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