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CD74HC192PWTE4 データシート(PDF) 10 Page - Texas Instruments |
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CD74HC192PWTE4 データシート(HTML) 10 Page - Texas Instruments |
10 / 20 page 10 FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL) FIGURE 8. CASCADED UP/DOWN COUNTER WITH PARALLEL LOAD NOTE: Illegal states in BCD counters corrected in one count. NOTE: Illegal states in BCD counters corrected in one or two counts. FIGURE 9. ’HC192, ’HCT193 STATE DIAGRAMS Test Circuits and Waveforms (Continued) INPUT LEVEL INPUT LEVEL Q = p VS tH tSU(L) Q = p Qn PL Pn tSU(H) VS VS tH P0 P1 P2 P3 TCU TCD MR Q0 Q1 Q2 Q3 CPU CPD PL UP CLOCK DOWN CLOCK ASYNCHRONOUS, PARALLEL LOAD RESET OUTPUT CARRY BORROW DATA INPUT P0 P1 P2 P3 TCU TCD MR Q0 Q1 Q2 Q3 CPU CPD PL 234 5 6 7 8 9 10 11 12 13 14 15 1 0 COUNT UP 234 5 6 7 8 9 10 11 12 13 14 15 1 0 COUNT DOWN |
同様の部品番号 - CD74HC192PWTE4 |
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同様の説明 - CD74HC192PWTE4 |
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