データシートサーチシステム |
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FM24C64 データシート(PDF) 7 Page - Ramtron International Corporation |
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FM24C64 データシート(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C64 Rev. 3.0 Mar. 2005 7 of 12 S DEVICE ADDRESS 1 By Master By FM24C64 Start Stop A Acknowledge DATA BYTE P Address Data No Acknowledge 1 Figure 7. Current Address Read S DEVICE ADDRESS 1 By Master By FM24C64 Start Stop A Acknowledge DATA BYTE 1 P Address No Acknowledge Data Acknowledge A DATA BYTE A DATA BYTE Figure 8. Sequential Read By Master By FM24C64 Stop DATA BYTE 1 P No Acknowledge A S DEVICE ADDRESS 0 Start A Acknowledge Address ADDRESS MSB A Data Acknowledge XX X ADDRESS LSB A S DEVICE ADDRESS 1 Start A DATA BYTE Figure 9. Selective (Random) Read Endurance Internally, a FRAM operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The FRAM architecture is based on an array of rows which are subdivided into segments. Rows (defined by A12-A5) are subdivided into 4 segments (A4-A3). Each access causes an endurance cycle for a row segment. In the FM24C64, there are 8 bytes (defined by A2-A0) per segment. Endurance can be optimized by ensuring frequently accessed data is located in different segments. Regardless, FRAM read and write endurance is effectively unlimited at the 1MHz two- wire speed. Even at 3000 accesses per second to the same segment, 10 years time will elapse before 1 trillion endurance cycles occur. |
同様の部品番号 - FM24C64 |
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同様の説明 - FM24C64 |
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