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FM25040A-S データシート(PDF) 5 Page - Ramtron International Corporation

部品番号 FM25040A-S
部品情報  4Kb FRAM Serial Memory
Download  13 Pages
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メーカー  RAMTRON [Ramtron International Corporation]
ホームページ  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25040A-S データシート(HTML) 5 Page - Ramtron International Corporation

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FM25040A
Rev. 3.0
May 2006
Page 5 of
13
Data Transfer
All data transfers to and from the FM25040A occur
in 8-bit groups. They are synchronized to the clock
signal (SCK) and they transfer most significant bit
(MSB) first. The serial input data is clocked in on
the rising edge of SCK. The serial data output is
driven from the falling edge of SCK.
Command Structure
There are six commands called op-codes that can be
issued by the bus master to the FM25040A. They are
listed in the table below. These op-codes control the
functions performed by the memory. They can be
divided
into
three
categories.
First,
there
are
commands that have no subsequent data transfer.
They perform a single function, such as, enabling a
write operation. Second are commands followed by
one byte, either in or out. They operate on the status
register.
Third
are
commands
for
memory
transactions followed by address and one or more
bytes of data.
Table 1. Op-code Commands
Name
Description
Op-code
WREN
Set Write Enable Latch
0000_0110b
WRDI
Write Disable
0000_0100b
RDSR
Read Status Register
0000_0101b
WRSR
Write Status Register
0000_0001b
READ
Read Memory Data
0000_A011b
WRITE
Write Memory Data
0000_A010b
WREN - Set Write Enable Latch
The FM25040A will power up with writes disabled.
The WREN command must be issued prior to any
write operation. Sending the WREN op-code will
allow the user to issue subsequent op-codes for
write operations. These include writing the status
register and writing the memory.
Sending the WREN op-code causes the internal
Write Enable Latch to be set. A flag bit in the status
register, called WEL, indicates the state of the latch.
WEL=1 indicates that writes are permitted. A write
to the status register has no effect on the WEL bit.
Completing any write operation will automatically
clear the write-enable latch and prevent further
writes without another WREN command. Figure 5
below
illustrates
the
WREN
command
bus
configuration.
WRDI - Write Disable
The WRDI command disables all write activity by
clearing the Write Enable Latch. The user can verify
that writes are disabled by reading the WEL bit in
the status register and verifying that WEL=0. Figure
6 illustrates the WRDI command bus configuration.
Figure 6. WRDI Bus Configuration
Figure 5. WREN Bus Configuration


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