CAT25010VE-GT3 datasheet(6/17 Pages) CATALYST

部品番号	CAT25010VE-GT3

部品情報	1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM

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メーカー	CATALYST [Catalyst Semiconductor]

ホームページ	http://www.catalyst-semiconductor.com

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CAT25010, CAT25020, CAT25040

Doc. No. MD-1006 Rev. T

6

Characteristics subject to change without notice

WRITE OPERATIONS

The CAT25010/20/40 device powers up into a write

disable state. The device contains a Write Enable

Latch (WEL) which must be set before attempting to

write to the memory array or to the status register. In

addition, the address of the memory location(s) to be

written must be outside the protected area, as defined

by BP0 and BP1 bits from the status register.

Write Enable and Write Disable

The internal Write Enable Latch and the corresponding

Status Register WEL bit are set by sending the WREN

instruction to the CAT25010/20/40. Care must be taken

to take the CS

¯¯ input high after the WREN instruction,

as otherwise the Write Enable Latch will not be

properly set. WREN timing is illustrated in Figure 2.

The WREN instruction must be sent prior any WRITE

or WRSR instruction.

The internal write enable latch is reset by sending the

WRDI instruction as shown in Figure 3. Disabling write

operations by resetting the WEL bit, will protect the

device against inadvertent writes.

Figure 2. WREN Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

Figure 3. WRDI Timing

Note:

Dashed Line = mode (1, 1) - - - - - -

SCK

SI

CS

SO

000

0

11

0

HIGH IMPEDANCE

SCK

SI

CS

SO

0

000

10

0

HIGH IMPEDANCE

同様の部品番号 - CAT25010VE-GT3

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ON Semiconductor	CAT25010VE-GT3	185Kb / 15P	1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM February, 2010 ??Rev. 21
ON Semiconductor	CAT25010VE-GT3	198Kb / 18P	1-Kb, 2-Kb and 4-Kb SPI Serial CMOS EEPROM January, 2012 ??Rev. 23

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