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74LVTH162374MEX データシート(PDF) 6 Page - Fairchild Semiconductor

部品番号 74LVTH162374MEX
部品情報  Low Voltage 16-Bit D-Type Flip-Flop with 3-STATE Outputs and 25廓 Series Resistors in the Outputs
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74LVTH162374MEX データシート(HTML) 6 Page - Fairchild Semiconductor

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©2000 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74LVTH162374 Rev. 1.0.0
6
Dynamic Switching Characteristics(6)
Note:
6. Characterized in SSOP package. Guaranteed parameter, but not tested.
7. Max number of outputs defined as (n). n–1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
Note:
8. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance(9)
Note:
9. Capcitance is measured at frequency f = 1MHz, per MIL-STD-883, Method 3012.
Symbol
Parameter
VCC
(V)
Conditions
CL = 50pF,
RL = 500Ω
TA = -40°C to +85°C
Units
Min.
Typ.
Max
VOLP
Quiet Output Maximum Dynamic VOL
3.3
(7)
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
3.3
(7)
-0.8
V
Symbol
Parameter
TA = -40°C to +85°C,
CL = 50pF, RL = 500Ω
Units
VCC = 3.3V ±0.3V
VCC = 2.7V
Min.
Max.
Min.
Max.
fMAX
Maximum Clock Frequency
160
150
MHz
tPHL
tPLH
Propagation Delay, CP to On
2.0
1.6
5.1
5.3
2.0
1.6
5.3
6.2
ns
tPZL
tPZH
Output Enable Time
1.8
1.2
5.0
5.6
1.8
1.2
6.0
6.9
ns
tPLZ
tPHZ
Output Disable Time
1.9
2.0
5.0
5.4
1.9 2.0
5.1
5.7
ns
tS
Setup Time
1.8
2.0
ns
tH
Hold Time
0.8
0.1
ns
tW
Pulse Width
3.0
3.0
ns
tOSHL
tOSLH
Output to Output Skew(8)
1.0
1.0
1.0
1.0
ns
Symbol
Parameter
Conditions
Typ.
Units
CIN
Input Capacitance
VCC = OPEN, VI = 0V or VCC
4pF
CPD
Power Dissipation Capacitance
VCC = 3.0V, VO = 0V or VCC
8pF


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