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ML12511 データシート(PDF) 6 Page - LANSDALE Semiconductor Inc.

部品番号 ML12511
部品情報  MECL PLL Components Dual Modulus Prescaler
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メーカー  LANSDALE [LANSDALE Semiconductor Inc.]
ホームページ  http://www.lansdale.com
Logo LANSDALE - LANSDALE Semiconductor Inc.

ML12511 データシート(HTML) 6 Page - LANSDALE Semiconductor Inc.

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Page 6 of 12
Issue 0
LANSDALE Semiconductor, Inc.
ML12509, ML12511, ML12513
Figure 5. AC Test Circuit
All Pulse Generators are EH 137 or equiv.
Pulse
Generator
#4
Pulse Generators 1, 2 and 4:
PRF = 10 MHz
PW = 50% Duty Cycle
t + = t – = 2.0
± 0.2 ns
Pulse Generator 3:
PRF = 2.0 MHz
PW = 50% Duty Cycle
t + = t – = 5.0
± 0.5 ns
All resistors are +1%.
All input and output cables to the scope are equal lengths of 50
Ω coaxial cable.
The 1950
Ω resistor at Pin 7 and the scope termination impedance constitute a 40 :1 attenuator probe.
CT = 15 pF = total parasitic capacitance which includes probe, wiring, and load capacitance.
Unused output connected to a 50
Ω resistor to ground.
Vin
50
100
Vin
Pulse
Generator
#1
Pulse
Generator
#2
Pulse
Generator
#3
A
MC10109 or equiv.
(Scope Channel A)
50
950
VCC = 2.0 V
25
µF
13
12
11
10
9
15
14
5
4
0.1
µF
+
VEE = –3.0 V
8
MECL
to
MTTL
Trans–
lator
VBB
C
E5
E4
E3
E2
E1
16
16
0.1
µF
2
3
7
VEE = –3.0 V
CT
1950
Vout
Vout (Scope Channel B)
Q
Q
50
100
Vin
50
Vin
Vout
NOTES: 1. Test outputs of the device must be tested by sequencing through the truth table. All input, power supply and
ground voltages must be maintained between tests. The clock input is the waveform shown.
2. In addition to meeting the output levels specified, the device must divide by 5 or 8 during this test. The clock
input is the waveform shown.
3. In addition to meeting the output levels specified, the device must divide by 6 or 9 during this test. The clock
input is the waveform shown.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50
Ω resistor to –2.0 V. Test procedures are shown for only one gate. The other gates are tested in the same
manner.
VIHmax
VILmin
Clock Input


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