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DAC8806IDB データシート(PDF) 3 Page - Texas Instruments |
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DAC8806IDB データシート(HTML) 3 Page - Texas Instruments |
3 / 20 page www.ti.com ELECTRICAL CHARACTERISTICS DAC8806 SBAS385A – APRIL 2006 – REVISED JUNE 2006 All specifications at –40 °C to +85°C, V DD = +2.7V to +5.5V, IOUT = virtual GND, GND = 0V, VREF = 10V, and TA = full operating temperature, unless otherwise noted. DAC8806 PARAMETER CONDITIONS MIN TYP MAX UNITS STATIC PERFORMANCE Resolution 14 Bits Relative accuracy DAC8806 ±1 LSB Differential nonlinearity ±0.5 ±1 LSB Output leakage current Data = 0000h, TA = +25°C 5 nA Output leakage current Data = 0000h, TA = TMAX 10 nA Full-scale gain error Unipolar, data = 3FFFh 1 ±4 LSB Bipolar, data = 3FFFh 1 ±4 LSB Full-scale temperature coefficient 1 2 ppm/ °C Bipolar zero scale error ±1 ±3 LSB PSRR Power-supply rejection ratio; VDD = 5V ±10% ±0.1 ±1 LSB/V OUTPUT CHARACTERISTICS(1) Output current 1.66 mA Output capacitance Code dependent 50 pF REFERENCE INPUT VREF range –15 15 V RREF Input resistance (unipolar) 4.5 6 7.5 k Ω Input capacitance 5 pF R1/R2 R1/R2 resistance (bipolar) 9 12 15 k Ω ROFS, RFB Feedback and offset resistance 9 12 15 k Ω LOGIC INPUTS AND OUTPUT(1) Input low voltage VIL VDD = +2.7V 0.6 V VIL VDD = +5V 0.8 V Input high voltage VIH VDD = +2.7V 2.1 V VIH VDD = +5V 2.4 V Input leakage current IIL 0.001 1 µA Input capacitance CIL 8 pF INTERFACE TIMING, VDD = +5.0V(1) (See Figure 40 and Table 1) tDS Data to WR setup time 20 ns tDH Data to WR hold time 0 ns tWR WR pulse width 20 ns tLDAC LDAC pulse width 20 ns Data setup time tRST RST pulse width 20 ns Data hold time tLWD WR to LDAC delay time 0 ns INTERFACE TIMING, VDD = +5.0V(1) (See Figure 40 and Table 1) tDS Data to WR setup time 35 ns tDH Data to WR hold time 0 ns tWR WR pulse width 35 ns tLDAC LDAC pulse width 35 ns Data setup time tRST RST pulse width 35 ns Data hold time tLWD WR to LDAC delay time 0 ns (1) Specified by design and characterization; not production tested. 3 Submit Documentation Feedback |
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同様の説明 - DAC8806IDB |
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