74ALVC574D datasheet(11/17 Pages) NXP

部品番号	74ALVC574D

部品情報	Octal D-type flip-flop; positive edge-trigger; 3-state

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74ALVC574_2

Product data sheet

Rev. 02 — 8 November 2007

11 of 17

NXP Semiconductors

74ALVC574

Octal D-type ﬂip-ﬂop; positive edge-trigger; 3-state

Test data is given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 10. Test circuit for switching times

VM

tW

10 %

90 %

0 V

VI

negative

pulse

positive

pulse

0 V

VM

90 %

10 %

tf

tr

tf

001aae331

VEXT

VCC

VI

VO

DUT

CL

RT

RL

G

Table 9.

Test data

Supply voltage

Input

Load

VEXT

VI

tr, tf

CL

RL

tPLH, tPHL

tPLZ, tPZL

tPHZ, tPZH

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

open

2VCC

GND

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

open

2VCC

GND

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

6 V

GND

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

6 V

GND

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