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74AVCH1T45GW データシート(PDF) 3 Page - NXP Semiconductors

部品番号 74AVCH1T45GW
部品情報  Dual supply translating transceiver; 3-state
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

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74AVCH1T45_1
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 25 October 2007
3 of 22
NXP Semiconductors
74AVCH1T45
Dual supply translating transceiver; 3-state
6.
Pinning information
6.1 Pinning
6.2 Pin description
7.
Functional description
[1]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
[2]
The DIR input circuit is referenced to VCC(A).
[3]
The input circuit of the data I/O is always active.
[4]
If at least one of VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.
Fig 3.
Pin configuration SOT363
Fig 4.
Pin configuration SOT886
74AVCH1T45
VCC(A)
VCC(B)
GND
AB
001aag887
1
2
3
6
DIR
5
4
74AVCH1T45
GND
001aag888
VCC(A)
A
DIR
VCC(B)
B
Transparent top view
2
3
1
5
4
6
Table 3.
Pin description
Symbol
Pin
Description
VCC(A)
1
supply voltage port A and DIR
GND
2
ground (0 V)
A
3
data input or output
B
4
data input or output
DIR
5
direction control
VCC(B)
6
supply voltage port B
Table 4.
Function table[1]
Supply voltage
Input
Input/output[3]
VCC(A), VCC(B)
DIR[2]
A
B
0.8 V to 3.6 V
L
A = B
input
0.8 V to 3.6 V
H
input
B = A
GND[4]
XZ
Z


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