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74LVC1G18 データシート(PDF) 8 Page - NXP Semiconductors

部品番号 74LVC1G18
部品情報  1-of-2 non-inverting demultiplexer with 3-state deselected output
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC1G18 データシート(HTML) 8 Page - NXP Semiconductors

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74LVC1G18_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 30 August 2007
8 of 13
NXP Semiconductors
74LVC1G18
1-of-2 non-inverting demultiplexer with 3-state deselected output
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 5.
Load circuitry for switching times
VEXT
VCC
VI
VO
mna616
DUT
CL
RT
RL
RL
G
Table 10.
Test data
VCC
Input
Load
VEXT
VI
tr =tf
CL
RL
tPLH, tPHL
tPZH, tPHZ
tPZL, tPLZ
1.65 V to 1.95 V
VCC
≤ 2.0 ns
30 pF
1 k
open
GND
2
× VCC
2.3 V to 2.7 V
VCC
≤ 2.0 ns
30 pF
500
open
GND
2
× VCC
2.7 V
2.7 V
≤ 2.5 ns
50 pF
500
open
GND
6 V
3.0 V to 3.6 V
2.7 V
≤ 2.5 ns
50 pF
500
open
GND
6 V
4.5 V to 5.5 V
VCC
≤ 2.5 ns
50 pF
500
open
GND
2
× VCC


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