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74LVC1G79 データシート(PDF) 8 Page - NXP Semiconductors |
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74LVC1G79 データシート(HTML) 8 Page - NXP Semiconductors |
8 / 16 page 74LVC1G79_7 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 07 — 29 August 2007 8 of 16 NXP Semiconductors 74LVC1G79 Single D-type flip-flop; positive-edge trigger fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 12. Waveforms Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 7. Clock (CP) to output (Q) propagation delay times mna443 CP input Q output tPHL tPLH VM VM VOH VI GND D input VI GND VOL VM VM Measurement points are given in Table 9. VOL and VOH are typical output voltage levels that occur with the output. Fig 8. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold times and maximum clock pulse frequency mna647 th tsu th tPHL tW tPLH tsu 1/fmax VM VM VM VI GND VI GND CP input D input VOH VOL Q output |
同様の部品番号 - 74LVC1G79 |
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同様の説明 - 74LVC1G79 |
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