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74LVC2G02DC データシート(PDF) 1 Page - NXP Semiconductors

部品番号 74LVC2G02DC
部品情報  Dual 2-input NOR gate
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo NXP - NXP Semiconductors

74LVC2G02DC データシート(HTML) 1 Page - NXP Semiconductors

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1.
General description
The 74LVC2G02 provides a 2-input NOR gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2.
Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant outputs for interfacing with 5 V logic
s High noise immunity
s
±24 mA output drive (V
CC = 3.0 V)
s CMOS low power consumption
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s ESD protection:
x HBM EIA/JESD22-A114E exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s Multiple package options
s Specified from
−40 °C to +85 °C and −40 °C to +125 °C
74LVC2G02
Dual 2-input NOR gate
Rev. 05 — 4 September 2007
Product data sheet


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