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74LVC4066 データシート(PDF) 4 Page - NXP Semiconductors |
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74LVC4066 データシート(HTML) 4 Page - NXP Semiconductors |
4 / 22 page 74LVC4066_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 27 August 2007 4 of 22 NXP Semiconductors 74LVC4066 Quad bilateral switch 6. Functional description [1] H = HIGH voltage level; L = LOW voltage level. 7. Limiting values [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed. [3] For SO14 packages: above 70 °C derate linearly with 8 mW/K. For (T)SSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. Table 3. Function table[1] Input nE Switch L OFF HON Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage −0.5 +6.5 V VI input voltage [1] −0.5 +6.5 V IIK input clamping current VI < −0.5 V or VI <VCC + 0.5 V −50 - mA ISK switch clamping current VI < −0.5 V or VI <VCC + 0.5 V - ±50 mA VSW switch voltage enable and disable mode [2] −0.5 +6.5 V ISW switch current −0.5 < VSW < VCC + 0.5 V - ±50 mA ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation Tamb = −40 °C to +125 °C [3] - 500 mW |
同様の部品番号 - 74LVC4066 |
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同様の説明 - 74LVC4066 |
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