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SM5816AF データシート(PDF) 2 Page - Nippon Precision Circuits Inc |
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SM5816AF データシート(HTML) 2 Page - Nippon Precision Circuits Inc |
2 / 27 page SM5816AF SEIKO NPC CORPORATION —2 PIN DESCRIPTION No. Name I/O Property1 Output current Input voltage Description 1 VDD1 – – – – Supply pin 1 2 MSHIFT I S – 3.3/5 Serial control: shift clock 3 MLATCH I S – 3.3/5 Serial control: latch clock 4 MDATA I S – 3.3/5 Serial control: command data 5 DSGAIN I PD – 3.3/5 DSD signal gain setting L: 100% modulation = 0dB, H: 50% modulation = 0dB 6 SELSBSW I PD – 3.3/5 DSD-SW input to SW/(SBL, SBR) output select L: SW input to SW output, H: SW input to (SBL, SBR) output Note. It effects both of DSD and 8fs outputs. 7 SELSBR I PD – 3.3/5 DSD 8fs-(SBL, SBR) output select L: SBL output only, H: both SBL, SBR output Note: Valid only when SELSBSW is HIGH. 8 SELMCU I PD – 3.3/5 Control method select L: pin control, H: serial interface data control 9 MONTOR O – 2mA – Parameter change monitor output 10 VSS1 – – – – Ground pin 1 11 DSBCKB I/O S 6mA 3.3/5 DSD through-mode data output: bit clock, controlled by DIRDSCK1, 2 12 DSOSR O – 2mA – DSD through-mode data output: surround right-channel 13 DSOSL O – 2mA – DSD through-mode data output: surround left-channel 14 DSOSBR O – 2mA – DSD through-mode data output: surround back right-channel 15 DSOSBL O – 2mA – DSD through-mode data output: surround back left-channel 16 DSOSW O – 2mA – DSD through-mode data output: subwoofer channel 17 DSOCT O – 2mA – DSD through-mode data output: center channel 18 DSOFR O – 2mA – DSD through-mode data output: front right-channel 19 DSOFL O – 2mA – DSD through-mode data output: front left-channel 20 VSS2 – – – – Ground pin 2 21 VDD2 – – – – Supply pin 2 22 DIR8CK I PD – 3.3/5 8fs output F8BCK, F8WCK input/output select L: output (master mode), H: Input (slave mode) 23 FMT8FS I PD – 3.3/5 8fs PCM format (MSB-first) L: MSB-first left-justified 32-bit, H: MSB-first right-justified 24-bit Note: In 8fs right-justified 24-bit format, there are a fixed 32 bit clock (F8BCK) cycles per word clock (F8WCK) cycle. Note: In 8fs right-justified 24-bit format, the upper empty bits are for sign extension. 24 FMT8WCK I PD – 3.3/5 8fs PCMWCK format L: “H” → “L” (rising-edge word boundary) H: “L” → “H” (falling edge word boundary) 25 F8BCK I/O S 6mA 3.3/5 8fs PCM BCK (bit clock) 26 F8WCK I/O S 6mA 3.3/5 8fs PCM WCK (word clock) 27 F8SR O – 2mA – 8fs PCM data output: surround right-channel 28 F8SL O – 2mA – 8fs PCM data output: surround left-channel 29 F8SBR O – 2mA – 8fs PCM data output: surround back right-channel 30 VSS3 – – – – Ground pin 3 31 VDD3 – – – – Supply pin 3 32 F8SBL O – 2mA – 8fs PCM data output: surround back left-channel 33 F8SW O – 2mA – 8fs PCM data output: subwoofer channel 34 F8CT O – 2mA – 8fs PCM data output: center channel |
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