TC59LM836DKB-33 datasheet(7/65 Pages) TOSHIBA

部品番号	TC59LM836DKB-33

部品情報	MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 288Mbits Network FCRAM2

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メーカー	TOSHIBA [Toshiba Semiconductor]

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7 / 65 page

TC59LM836DKB-30,-33,-40

2005-03-07

7/65

Rev 1.3

RECOMMENDED DC OPERATING CONDITIONS

(VDD = 2.5 V ± 0.125 V, VDDQ = 1.4 V ~ 1.9 V, TCASE = 0 ~ 85°C)

MAX

SYMBOL

PARAMETER

-30

-33

-40

UNIT

NOTES

IDD1S

Operating Current

One bank read or write operation ;

tCK = min; IRC = min, IOUT = 0mA ;

Burst Length

= 4, CAS Latency = 6, Free running QS mode ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,

Address inputs change up to 2 times during minimum IRC,

Read data change twice per clock cycle

380

360

340

1, 2

IDD2N

Standby Current

All banks: inactive state ;

tCK = min, CS = VIH, PD = VIH ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;

Other input signals change one time during 4

× tCK,

DQ and DS inputs change twice per clock cycle

120

110

100

1, 2

IDD2P

Standby (power down) Current

All banks: inactive state ;

tCK = min, PD = VIL (power down) ;

CAS Latency

= 6, Free running QS mode ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;

Other input signals change one time during 4

× tCK,

DQ and DS inputs are floating (VDDQ/2)

100

95

90

1, 2

IDD4W

Write Operating Current (4Banks)

4 Bank interleaved continuous burst write operation ;

tCK = min, IRC = min ;

Burst Length

= 4, CAS Latency = 6, Free running QS mode ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;

Address inputs change once per clock cycle,

DQ and DS inputs change twice per clock cycle

850

800

750

1, 2

IDD4R

Read Operating Current (4Banks)

4 Bank interleaved continuous burst read operation ;

tCK = min, IRC = min, IOUT = 0mA ;

Burst Length

= 4, CAS Latency = 6, Free running QS mode ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ ;

Address inputs change once per clock cycle,

Read data change twice per clock cycle

850

800

750

1, 2

IDD5B

Burst Auto Refresh Current

Refresh command at every IREFC interval ;

tCK = min; IREFC = min ;

CAS Latency

= 6, Free running QS mode ;

0 V

≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,

Address inputs change up to 2 times during minimum IREFC,

DQ and DS inputs change twice per clock cycle

380

360

340

1, 2, 3

IDD6

Self-Refresh Current

PD

= 0.2 V ;

Other input signals are floating (VDDQ/2),

DQ and DS inputs are floating (VDDQ/2)

15

mA

2

Notes: 1.

These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of

tCK, tRC and IRC.

2. These parameters define the current between VDD and VSS.

3. IDD5B is specified under burst refresh condition. Actual system should use distributed refresh that meet to tREFI

specification.

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