TC74HC107AF datasheet(1/9 Pages) TOSHIBA

部品番号	TC74HC107AF

部品情報	CMOS Digital Integrated Circuit Silicon Monolithic Dual J-K Flip Flop with Clear

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メーカー	TOSHIBA [Toshiba Semiconductor]

ホームページ	http://www.semicon.toshiba.co.jp/eng

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TC74HC107AP/AF/AFN

2007-10-01

1

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74HC107AP,TC74HC107AF,TC74HC107AFN

Dual J-K Flip Flop with Clear

The TC74HC107A is a high speed CMOS DUAL J-K FLIP

FLOP fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent

LSTTL while maintaining the CMOS low power dissipation.

In accordance with the logic levels applied to the J and K

inputs, the outputs change state on the negative going transition

of the clock pulse.

CLR is independent of the clock and is accomplished by a low

logic level on the input.

All inputs are equipped with protection circuits against static

discharge or transient excess voltage.

Features

• High speed: fmax = 75 MHz (typ.) at VCC = 5 V

• Low power dissipation: ICC = 2 μA (max) at Ta = 25°C

• High noise immunity: VNIH = VNIL = 28% VCC (min)

• Output drive capability: 10 LSTTL loads

• Symmetrical output impedance: |IOH| = IOL = 4 mA (min)

• Balanced propagation delays: tpLH ∼− tpHL

• Wide operating voltage range: VCC (opr) = 2~6 V

• Pin and function compatible with 74LS107

Pin Assignment

IEC Logic Symbol

Note: xxxFN (JEDEC SOP) is not available in

Japan.

TC74HC107AP

TC74HC107AF

TC74HC107AFN

Weight

DIP14-P-300-2.54

: 0.96 g (typ.)

SOP14-P-300-1.27A

: 0.18 g (typ.)

SOL14-P-150-1.27

: 0.12 g (typ.)

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