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TC74HC423AF データシート(PDF) 4 Page - Toshiba Semiconductor |
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TC74HC423AF データシート(HTML) 4 Page - Toshiba Semiconductor |
4 / 12 page TC74HC423AP/AF 2007-10-01 4 Timing Chart Functional Description (1) Stand-by state The external capacitor Cx is fully charged to VCC in the stand-by state. That means, before triggering, the QP and QN transistors which are connected to the Rx/Cx node are in the off state. Two comparators that relate to the timing of the output pulse, and two reference voltage supplies turn off. The total supply current is only leakage current. (2) Trigger operation Trigger operation is effective in either of the following two cases. First, the condition where the A input is low, and the B input has a rising signal; second, where the B input is high, and the A input has a falling signal. After a trigger becomes effective, comparators C1 and C2 start operating, and QN is turned on. The external capacitor discharges through QN. The voltage level of the Rx/Cx node drops. If the Rx/Cx voltage level falls to the internal reference voltage Vref L, the output of C1 becomes low. The flip-flop is then reset and QN turns off. At that moment C1 stops but C2 continues operating. After QN turns off, the voltage at the Rx/Cx starts rising at a rate determined by the time constant of external capacitor Cx and resistor Rx. Upon the triggering, output Q becomes high, following some delay time of the internal F/F and gates. It stays high even if the voltage of Rx/Cx changes from falling to rising. When Rx/Cx reaches the internal reference voltage Vref H, the output of C2 becomes low, the output Q goes low and C2 stops its operation. That means, after triggering, when the voltage level of the Rx/Cx reaches Vref H, the IC returns to its MONOSTABLE state. With large values of Cx and Rx, and ignoring the discharge time of the capacitor and internal delays of the IC, the width of the output pulse, tw (OUT), is as follows: tw (OUT) = 1.0・Cx・Rx (3) Retrigger operation When a new trigger is applied to input A or B while in the MONOSTABLE state, it is effective only if the IC is charging Cx. The voltage level of the Rx/Cx node then falls to Vref L level again. Therefore the Q output stays high if the next trigger comes in before the time period set by Cx and Rx. If the 2nd trigger is very close to previous trigger, such as an occurrence during the discharge cycle, it will have no effect. The minimum time for a trigger to be effective 2nd trigger, trr (min), depends on VCC and Cx. (4) Reset operation In normal operation, CLR input is held high. If CLR is low, a trigger has no effect because the Q output is held low and the trigger control F/F is reset. Also, QP turns on and Cx is charged rapidly to VCC. This means if CLR input is set low, the IC goes into a wait state. |
同様の部品番号 - TC74HC423AF |
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同様の説明 - TC74HC423AF |
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