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TA48S018F データシート(PDF) 7 Page - Toshiba Semiconductor |
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TA48S018F データシート(HTML) 7 Page - Toshiba Semiconductor |
7 / 11 page TA48S018,02,025,03,033,05F 2006-11-06 7 Precaution on Application Tj = 25°C in the measurement conditions of each item is a regulation for where a pulse test is carried out and any drift in the electrical characteristic due to a rise in the junction temperature of the chip may be disregarded. Depending on the load conditions, a steep increase in the input voltage applied (VIN) may cause a momentary rise in output voltage (VOUT) even if the EN (enable) pin is Low. Treat with care. Standard Application Circuit Be sure to connect a capacitor near the input terminal and output terminal between both terminals and GND. The capacitances should be determined experimentally. In particular, adequate investigation should be made to ensure there are no problems even in high or low temperatures. CIN 0.33 μF IN OUT EN NC GND CPU etc. LOAD COUT 47 μF TA48S **F |
同様の部品番号 - TA48S018F |
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同様の説明 - TA48S018F |
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