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TC7MP245FTG データシート(PDF) 2 Page - Toshiba Semiconductor |
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TC7MP245FTG データシート(HTML) 2 Page - Toshiba Semiconductor |
2 / 12 page TC7MP245FK/FTG 2007-10-19 2 Pin Assighment (top view) Truth Table Marking Input DIR OE Bus state Bus hold circuit (B bus) L L B→A(B=A) OFF H L A→B(A=B) OFF X H Z ON* X: Don’t care Z: High impedance *: Logic state just before becoming disable is maintained. Note: When a bus input is in "H" state ,and an output is switched to "enable" to "disable", Glitch such as "L" state during about 1 to 3ns occurs in an output. It is not generated when a bus input is in "L" state. System Diagram A1 OE DIR B1 1/8 1 2 3 4 5 A2 A3 A4 A5 A6 6 7 8 9 10 15 14 13 12 11 A7 A8 GND B8 B7 B2 B3 B4 B5 B6 20 19 18 17 16 A1 DIR VCC B1 OE FK (VSSOP20-P-0030-0.50) VCC 20 OE B1 B2 B3 B4 19 18 17 16 15 14 DIR 1 2 3 4 5 6 7 A1 A2 A3 A4 A5 A6 B5 8 9 10 A7 A8 GND 13 12 11 B6 B7 B8 FTG (VQON20-P-0404-0.50) P 0 0A ** * * Product Name Lot trace code FTG (VQON20-P-0404-0.50) 1 pin |
同様の部品番号 - TC7MP245FTG |
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同様の説明 - TC7MP245FTG |
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