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TC9349AFG データシート(PDF) 5 Page - Toshiba Semiconductor |
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TC9349AFG データシート(HTML) 5 Page - Toshiba Semiconductor |
5 / 129 page TC9349AFG 2006-02-24 5 Description of Pin Functions PIN No. Symbol Pin Name Function and Operation Remarks 64 Xin1 1 Xout1 Crystal oscillator pin Crystal oscillator pins. A reference 75 kHz crystal resonator is connected to the Xin1 and Xout1 pins. 68 GND 2 VDD Power-supply pins Power supply pin for the crystal oscillator and doubler circuit for the CPU (VDB). Normally, VDD = 0.9 to 1.8 V is applied. VDD potential is detected in the 0.850 V to 1.225 V range in 25 mV steps using the decreased voltage detection circuit. If VDD potential falls below the voltage being set, the CPU can be stopped to prevent incorrect operation. Note: After reset, the voltage set for the decreased voltage detection is VDD = 0.85 V. CPU stop function is enabled. 3 C1 ⎯ 4 C2 ⎯ 5 VDB Doubler output pins for CPU Doubler output pins for CPU. The doubler system is the charge-pump system. When a doubler clamp is permitted, a voltage of 2.0 V, 2.5 V or 3.0 V can be selected. A doubler clock can select either one of 75 kHz, 37.5 kHz or high-speed oscillator clock. Usually, the VDB pin connected to the capacitor for stabilization (0.1 µF, 10 µF typ.) supplies voltage for the power supply of the CPU only ( VCPU). The VDB potential is supplied to the power supply of the A/D converter, and a 1.5 V constant-voltage circuit ( VEE). The voltage is doubled by the doubler capacitor between C1 and C2 (0.47 µF typ.). When the doubler clamp is enabled, the voltage is doubled below the voltage being set. Note: During reset or execution of the clock stop instruction, the VDB pin is set to VDD level. The LX pin is L level for CMOS output, and at high impedance for open-drain output. Xout1 Xin1 Rout1 RfXT1 (Xin1, Xout1) VDD GND VDD VDB |
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