データシートサーチシステム |
|
LM1276AAA データシート(PDF) 11 Page - National Semiconductor (TI) |
|
|
LM1276AAA データシート(HTML) 11 Page - National Semiconductor (TI) |
11 / 50 page Typical Performance Characteristics V CC = 5V, TA = 25˚C unless otherwise specified (Continued) SYSTEM INTERFACE SIGNALS The Horizontal Sync, Flyback, Vertical Sync, and the Clamp input signals are important for proper functionality of the LM1276. Both blanking inputs must be present for OSD synchronization. In addition, the Horizontal blanking input also assists in setting the proper cathode black level, along with the Clamping pulse. The Vertical blanking input initiates a blanking level at the LM1276 outputs, which is program- mable from 3 to 127 lines (at least 10 is recommended). This input is set up to only accept a vertical sync pulse, and the leading edge is used to start the programmable vertical blanking signal directly. The start position of the internal Horizontal blanking pulse is programmable from 0 to 64 pixels ahead of the start position of the Horizontal flyback input. Both horizontal and vertical blanking can be individu- ally disabled, if desired. Figure 3 and Figure 4 show the Horizontal Flyback input when it is logic level and the Vertical input (which must always be logic level). Figure 3 shows the smaller pin 28 voltage superimposed on the horizontal blanking pulse input to the neck board with R H = 4.7k and C1 = 0.1 µF. Note where the voltage at pin 28 is clamped to about 1V when the pin is sinking current. Figure 4 shows the smaller pin 1 voltage superimposed on the vertical blanking input to the neck board with R V = 4.7k. These component values corre- spond to the application circuit of Figure 9. Please note that the Horizontal Flyback signal to pin 28 MUST be continuously provided to the IC, even during en- ergy save or sleep modes. In the application, this signal should be always generated whether the VGA cable is dis- connected, the monitor is in energy save mofe, or sleep mode. Figure 5 show the case where the horizontal input is from deflection. Figure 5 shows the pin 28 voltage which is de- rived from a horizontal flyback pulse of 35V peak to peak with R H = 8.2K and C1 jumpered. Figure 6 shows the pin 27 clamp input voltage superimposed on the neck board clamp logic input pulse.R=1kand should be chosen to limit the pin 27 voltage to about 2.5V peak to peak. This corresponds to the application circuit given in Figure 9. The clamp input pin can also be internally con- nected to the Horizontal Sync pin, thus eliminating the need for a Clamp signal supplied to the neckboard. This can be enabled with register 0x853E[4]. H SYNC & V SYNC V Sync at pin 1 and H Sync at pin 15 must be supplied with logic level signals generated by the MCU. In an application where a logic level clamp pulse is used, the same signal can be used for the H Sync input. It is important that both V Sync and H Sync are always receiving signals, even during VGA cable disconnect, energy save mode, or sleep mode. CATHODE RESPONSE Figure 7 shows the response at the red cathode for the application circuit in Figures 9, 10. The input video rise time is 1.5 ns. The resulting leading edge has a 7.1 ns rise time and 7.6% overshoot, while the trailing edge has a 7.1 ns rise time and 6.9% overshoot using an LM2467 driver. ABL GAIN REDUCTION The ABL function reduces the contrast level of the LM1276 as the voltage on pin 26 is lowered from V CC to around 2V. Figure 8 shows the amount of gain reduction as the voltage is lowered from V CC (5.0V) to 2V. The gain reduction is small until V 26 reaches the knee around 3.7V, where the slope increases. Many system designs will require about 3 dB to 5 dB of gain reduction in full beam limiting. Additional attenu- ation is possible, and can be used in special circumstances. However, in this case, video performance such as video linearity and tracking between channels will tend to depart from normal specifications. The onset of ABL in the LM1276 is adjustable so that the amount of beam limiting can be varied, especially for larger Hi-Brite window displays where the contrast level is not desired to be reduced as much as a normal video display. The beam current limiting is 4-bit adjustable in steps of 80 µA each all the way up to a delta of 1.2 mA. The value of the ABL pull up resistor (R2) to the external +80V supply must be selected carefully such that the ABL threshold current will be at the desired maximum (i.e. 2 mA) when register 0x85C4 is at the lowest setting, 0x00. There are 4 different ABL current registers corresponding to 4 different ABL settings. Each setting or register (0x85C4 - 0x85C7) can be assigned a different ABL current threshold. ABL current register 0 can correspond to a minimal area of the screen being highlighted, and ABL current register 4 can correspond to the maximum area of the screen being high- lighted. This area is calculated by the HiBrite software, and the particular ABL register that is is to be activated is se- lected by the software. The values of each register are written by the MCU. www.national.com 11 |
同様の部品番号 - LM1276AAA |
|
同様の説明 - LM1276AAA |
|
|
リンク URL |
プライバシーポリシー |
ALLDATASHEET.JP |
ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |