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74LVQ02T データシート(PDF) 1 Page - STMicroelectronics |
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74LVQ02T データシート(HTML) 1 Page - STMicroelectronics |
1 / 8 page 74LVQ02 QUAD 2-INPUT NOR GATE ® February 1999 PIN CONNECTION AND IEC LOGIC SYMBOLS s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 3.3V s COMPATIBLE WITH TTL OUTPUTS s LOW POWER DISSIPATION: ICC =2 µA (MAX.) at TA =25 oC s LOW NOISE: VOLP = 0.3 V (TYP.) at VCC =3.3V s 75 Ω TRANSMISSION LINE DRIVING CAPABILITY s SYMMETRICAL OUTPUT IMPEDANCE: |IOH|=IOL = 12 mA (MIN) s PCI BUS LEVELS GUARANTEED AT 24mA s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V (1.2V Data Retention) s PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 02 s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The LVQ02 is a low voltage CMOS QUAD 2-INPUT NOR GATE fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for low power and low noise 3.3V applications. The internal circuit is composed of 3 stages including buffer output, which enables high noise immunity and stable output. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. ORDER CODES : 74LVQ02M 74LVQ02T M (Micro Package) T (TSSOP Package) 1/8 |
同様の部品番号 - 74LVQ02T |
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同様の説明 - 74LVQ02T |
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