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DLX1414 データシート(PDF) 2 Page - OSRAM GmbH

部品番号 DLX1414
部品情報  Intelligent Display Products
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メーカー  OSRAM [OSRAM GmbH]
ホームページ  http://www.osram.com
Logo OSRAM - OSRAM GmbH

DLX1414 データシート(HTML) 2 Page - OSRAM GmbH

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 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA
Appnote 15
www.infineon.com/opto • 1-888-Infineon (1-888-463-4636)
OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany
www.osram-os.com • +49-941-202-7178
2
May 31, 2000-12
Figure 2. Top view and pin outs
Packaging
Packaging consists of an injection-molded plastic lens which
covers five of the six “faces.” The assembled and tested sub-
strate is placed within the shell and the entire assembly is then
filled with a waterclear IC-grade epoxy.
This yields a very rugged part which is quite impervious to mois-
ture, shock and vibration. Although not “hermetic, the device will
easily withstand total immersion in water/detergent solutions.
Figure 3. Character set–DLX1414
Pin
Function
Pin
Function
1
D5 Data Input
7
GND
2
D4 Data Input
8
D0 Data Input (LSB)
3WR Write
9
D1 Data Input
4
A1 Digit Select
10
D2 Data Input
5
A0 Digit Select
11
D3 Data Input
6VCC
12
D6 Data Input (MSB)
1
2
3
4
5
6
12 11 10 9
8 7
digit digit digit digit
3
2
1
0
ASCII
CODE
D0
D1
D2
D3
0
0
0
0
0
1
0
0
0
1
0
1
0
0
2
1
1
0
0
3
0
0
1
0
4
1
0
1
0
5
0
1
1
0
6
1
1
1
0
7
0
0
0
1
8
1
0
0
1
9
0
1
0
1
A
1
1
0
1
B
0
0
1
1
C
1
0
1
1
D
0
1
1
1
E
1
1
1
1
F
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
D6 D5 D4 HEX
1. High=1 level. 2. Low=0 level. 3. Upon power up, device will initialize in a random state.
Table 1. Electrical inputs to the DLX1414
Operation
Multiplexed display systems sequentially read and display data
from a memory device. In synchronous systems, control cir-
cuitry must compare the location of data to be read to the loca-
tion or position of new data to be stored or displayed, i.e.,
synchronize before a Write can be done. This can be slow and
cumbersome.
Data entry in Intelligent Displays is asynchronous and may be
done in any random order. Loading data is similar to writing into
a RAM. Each digit has its own memory location and will display
until replaced by another code.
The waveforms in Figure 4 demonstrate the relationships of
the signals required to generate a Write cycle. (Check individ-
ual data sheet for minimum values.) As can be seen from the
waveforms, all signals are referenced from the rising or trailing
edge of Write.
General Design Considerations
Using positive true logic, address order is from right to left. For
left to right address order, use the ones complement or simple
inversion of the addresses.
Figure 4. Write cycle waveform
VCC
Positive supply +5 V
GND
Ground
D0–D6
Data lines
The seven data input lines are designed to
accept the first 128 ASCII characters.
See Figure 3 for the character set.
A0, A1
Address Lines
The address determines the digit position
to which the data will be written. Address
order is right to left for positive-true logic.
WR
Write (Active Low)
Data and address to be loaded must be
present and stable before and after the
trailing edge of write.
(See data sheet for timing info).
tAH
tW
tAS
tDS
tDH
4 V
2 V
0 V
4 V
2 V
0 V
4 V
2 V
0 V
WR
D 0–D6
A 0–A1


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