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DLX1414 データシート(PDF) 3 Page - OSRAM GmbH |
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DLX1414 データシート(HTML) 3 Page - OSRAM GmbH |
3 / 4 page 2000 Infineon Technologies Corp. • Optoelectronics Division • San Jose, CA Appnote 15 www.infineon.com/opto • 1-888-Infineon (1-888-463-4636) OSRAM Opto Semiconductors GmbH & Co. OHG • Regensburg, Germany www.osram-os.com • +49-941-202-7178 3 May 31, 2000-12 When using the DLX1414 on a separate display board with more than 6 inches of cable length, it may be necessary to buffer all inputs. This is most easily achieved with Hex non-inverting buffers such as the 74365. The object is to prevent transient current in the protection diodes. The buffers should be located on the display board near the dis- plays. Local power supply bypass capacitors are also needed in many cases. These should be 6 or 10 volt, tantalum type with 10 µF or greater capacitance. Low internal resistance is important due to current steps which result from the internal multiplexing of the displays. If small wire cables are used, good engineering practice is to calculate the wire resistance of the ground plus the +5 volt wires. More than 0.1 volt drop, (at 25 mA per digit worst case) should be avoided, since this loss is in addition to any inaccuracies or load regulation limitations of the power supply. The 5-volt power supply for the displays should be the same one supplying VCC to all logic devices which drive the display devices. If a separate supply must be used, then local buffers using hex, non-inverting gates should be used on all inputs and these buffers should be powered from the display power supply. This precaution is to avoid logic inputs higher than display VCC during power up or line transients. Interfacing the DLX1414 A general and straightforward interface circuit is shown in Figure 6. This scheme can easily interface to LP systems or any other systems which can provide the seven data lines, appropriate address and control lines. The DLX1414 does not have a chip enable input; therefore each display in a system requires its Write pulse be gated with appropriate address signals. Figure 7a shows the use of a 74154 decoder (4 lines to 16 lines) for up to a 64 char- acter display. Using the G1 input for display select (address select in a memory mapped system) and the G2 input to gate the Write signal. Another approach (Figure 7b and 7c) which minimizes logic for a 16 or 32 digit display takes advantage of decoding scheme of the 7442 decoder. Parallel l/O The parallel l/O device of a microprocessor can be con- nected easily to the circuit in Figure 6. One eight bit output port can provide the seven input data bits. Another eight bit output port can contain the address and control signals. Figure 5. Data loading table Figure 6. General interface circuit Figure 7. Gating the write pulse Data Input H L L Digit 3 See Character Set WR A1 A0 D6 D5 D4 D3 D2 D1 D0 L L L L L NC D D D C C C K B B B B A A E E NC NC NC X L L X L H X H H X L L X L L X L L X L L X L H X H L H H L H – L H L L – H H H H – L L L L – L L L L – L L L H – L H H L – H L L H – H L H H – Digit 2 Digit 1 Digit 0 Address B A A X=Don't care NC NC NC NC NC L NC=No change Digit Select Decoder D C B A Display Vcc GND D15 D12 WR A3 A2 2/ Display D11 D8 Display D7 D4 Display D3 D0 WR A0 A1 D0 – A6 WR WR WR Display Select 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 WR A2 A3 A4 A5 A4 A3 A2 WR Digit Select Digit Select to WR of Display WR A3 A2 to WR of Display to WR of Display G 1 G 2 A B C D D C B A D C B A Unused Unused 7c. 7b. 7a. 74154 7442 7442 |
同様の部品番号 - DLX1414 |
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同様の説明 - DLX1414 |
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