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74VHC174 データシート(PDF) 4 Page - STMicroelectronics

部品番号 74VHC174
部品情報  HEX D-TYPE FLIP FLOP WITH CLEAR
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

74VHC174 データシート(HTML) 4 Page - STMicroelectronics

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CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
T est Cond ition s
Val ue
Un it
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
CIN
Input Capacitance
4
10
10
pF
CPD
Power Dissipation
Capacitance (note 1)
29
pF
1) CPD isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD
• VCC • fIN +ICC/6 (per Flip-Flop)
AC ELECTRICAL CHARACTERISTICS (Input tr =tf =3 ns)
Symb ol
Parameter
Test Co nditi on
Val ue
Un it
VCC
(V)
CL
(pF )
TA =25
oC
-40 to 85
oC
Min.
Typ .
Max.
Min .
Max.
tPLH
tPHL
Propagation Delay Time
CK to Q
3.3
(*)
15
7.2
11.0
1.0
13.0
ns
3.3
(*)
50
9.7
14.5
1.0
16.5
5.0
(**)
15
4.9
7.2
1.0
8.5
5.0
(**)
50
6.4
9.2
1.0
10.5
tPHL
Propagation Delay Time
CLR to Q
3.3
(*)
15
7.4
11.4
1.0
13.5
ns
3.3
(*)
50
9.9
14.9
1.0
17.0
5.0
(**)
15
5.1
7.6
1.0
9.0
5.0
(**)
50
6.6
9.6
1.0
11.0
tw
CLR pulse Width
LOW
3.3
(*)
5.0
5.0
ns
5.0
(**)
5.0
5.0
tw
CK pulse Width
HIGH r LOW
3.3
(*)
5.0
5.0
ns
5.0
(**)
5.0
5.0
ts
Setup Time D to CK
HIGH or LOW
3.3
(*)
5.0
6.0
ns
5.0
(**)
4.5
4.5
th
Hold Time D to CK
HIGH or LOW
3.3
(*)
0.0
0.0
ns
5.0
(**)
0.5
0..5
tREM
Removal Time
CLR to CK
3.3
(*)
3.0
3.0
ns
5.0
(**)
2.5
2.5
fMAX
Maximum Clock
Frequency
3.3
(*)
15
95
150
80
MHz
3.3
(*)
50
55
85
50
5.0
(**)
15
130
175
110
5.0
(**)
50
90
120
80
(*) Voltage range is 3.3V
± 0.3V
(**) Voltage range is 5V
± 0.5V
74VHC174
4/10


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