74VHCT174ATTR datasheet(1/10 Pages) STMICROELECTRONICS

部品番号	74VHCT174ATTR

部品情報	HEX D-TYPE FLIP FLOP WITH CLEAR

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74VHCT174A

HEX D-TYPE FLIP FLOP WITH CLEAR

PRELIMINARY DATA

March 2000

s

HIGH SPEED:

fMAX =150 MHz (TYP.) at VCC =5V

s

LOW POWER DISSIPATION:

ICC =4

µA (MAX.) at TA =25 oC

s

COMPATIBLE WITH TTL OUTPUTS:

VIH =2V (MIN), VIL = 0.8V (MAX)

s

POWER DOWN PROTECTION ON INPUTS &

OUTPUTS

s

SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL = 8 mA (MIN)

s

BALANCED PROPAGATION DELAYS:

tPLH

≅ tPHL

s

OPERATING VOLTAGE RANGE:

VCC (OPR) = 4.5V to 5.5V

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 174

s

IMPROVED LATCH-UP IMMUNITY

s

LOW NOISE: VOLP = 0.8V (Max.)

DESCRIPTION

The 74VHCT174A is an advanced high-speed

CMOS HEX D-TYPE FLIP FLOP WITH CLEAR

fabricated with sub-micron silicon gate and

double-layer metal wiring C

2MOS technology.

Information signals applied to D inputs are

transfered to the Q outputs on the positive going

edge of the clock pulse.

When the CLEAR input is held low, the Q outputs

are held low independently of the other inputs.

Power down protection is provided on all inputs

and outputs and 0 to 7V can be accepted on

inputs with no regard to the supply voltage. This

device can be used to interface 5V to 3V.

All inputs

and

outputs are

equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

®

SOP

TSSOP

ORDER CODES

PACKAGE

T UBE

T & R

SOP

74VHCT174AM

74VHCT174AMTR

TSSOP

74VHCT174ATTR

1/10

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