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74ACT374MSA データシート(PDF) 2 Page - Fairchild Semiconductor |
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74ACT374MSA データシート(HTML) 2 Page - Fairchild Semiconductor |
2 / 14 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC374, 74ACT374 Rev. 1.5.0 2 Connection Diagram Pin Description Functional Description The AC/ACT374 consists of eight edge-triggered flip- flops with individual D-type inputs and 3-STATE true out- puts. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the con- tents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high imped- ance state. Operation of the OE input does not affect the state of the flip-flops. Logic Symbols IEEE/IEC Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE 3-STATE Output Enable Input O0–O7 3-STATE Outputs Inputs Outputs Dn CP OE On HL H LL L XX H Z |
同様の部品番号 - 74ACT374MSA |
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同様の説明 - 74ACT374MSA |
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