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74AUP1T45GW データシート(PDF) 3 Page - NXP Semiconductors |
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74AUP1T45GW データシート(HTML) 3 Page - NXP Semiconductors |
3 / 33 page 74AUP1T45_1 © NXP B.V. 2006. All rights reserved. Product data sheet Rev. 01 — 18 October 2006 3 of 33 NXP Semiconductors 74AUP1T45 Low-power dual supply translating transceiver; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description 7. Functional description [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [2] The DIR input circuit is referenced to VCC(A). [3] The input circuit of the data I/Os are always active. Fig 3. Pin configuration SOT363 (SC-88) Fig 4. Pin configuration SOT886 (XSON6) Fig 5. Pin configuration SOT891 (XSON6) 74AUP1T45 VCC(A) VCC(B) GND AB 001aae964 1 2 3 6 DIR 5 4 74AUP1T45 GND 001aae965 VCC(A) A DIR VCC(B) B Transparent top view 2 3 1 5 4 6 74AUP1T45 GND 001aae966 VCC(A) A DIR VCC(B) B Transparent top view 2 3 1 5 4 6 Table 3. Pin description Symbol Pin Description VCC(A) 1 supply voltage port A GND 2 ground (0 V) A 3 data input or output A B 4 data input or output B DIR 5 direction control DIR VCC(B) 6 supply voltage port B Table 4. Function table[1] Supply voltage Input[2] Input/output[3] VCC(A), VCC(B) DIR A B 1.1 V to 3.6 V L A = B input 1.1 V to 3.6 V H input B = A GND X suspend mode suspend mode |
同様の部品番号 - 74AUP1T45GW |
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同様の説明 - 74AUP1T45GW |
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