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AD6653-150EBZ データシート(PDF) 9 Page - Analog Devices

部品番号 AD6653-150EBZ
部品情報  IF Diversity Receiver
Download  80 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD6653-150EBZ データシート(HTML) 9 Page - Analog Devices

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AD6653
Rev. 0 | Page 9 of 80
SWITCHING SPECIFICATIONS
Table 4.
AD6653BCPZ-125
AD6653BCPZ-150
Parameter
Temperature
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
625
625
MHz
Conversion Rate1
DCS Enabled
Full
20
125
20
150
MSPS
DCS Disabled
Full
10
125
10
150
MSPS
CLK Period—Divide-by-1 Mode (tCLK)
Full
8
6.66
ns
CLK Pulse Width High (tCLKH)
Divide-by-1 Mode, DCS Enabled
Full
2.4
4
5.6
2.0
3.33
4.66
ns
Divide-by-1 Mode, DCS Disabled
Full
3.6
4
4.4
3.0
3.33
3.66
ns
Divide-by-2 Mode, DCS Enabled
Full
1.6
1.6
ns
Divide-by-3 Through Divide-by-8 Modes,
DCS Enabled
Full
0.8
0.8
ns
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Noninterleaved Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
Full
1.6
3.9
6.2
1.6
3.9
6.2
ns
DCO Propagation Delay (tDCO)
Full
4.0
5.4
7.3
4.0
5.4
7.3
ns
Setup Time (tS)
Full
9.5
8.16
ns
Hold Time (tH)
Full
6.5
5.16
ns
CMOS Noninterleaved Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
Full
1.9
4.1
6.4
1.9
4.1
6.4
ns
DCO Propagation Delay (tDCO)
Full
4.4
5.8
7.7
4.4
5.8
7.7
ns
Setup Time (tS)
Full
9.7
8.36
ns
Hold Time (tH)
Full
6.3
4.96
ns
CMOS Interleaved and IQ Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
Full
1.6
3.9
6.2
1.6
3.9
6.2
ns
DCO Propagation Delay (tDCO)
Full
3.4
4.8
6.7
3.4
4.8
6.7
ns
Setup Time (tS)
Full
4.9
4.23
ns
Hold Time (tH)
Full
3.1
2.43
ns
CMOS Interleaved and IQ Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 2
Full
1.9
4.1
6.4
1.9
4.1
6.4
ns
DCO Propagation Delay (tDCO)
Full
3.8
5.2
7.1
3.8
5.2
7.1
ns
Setup Time (tS)
Full
5.1
4.43
ns
Hold Time (tH)
Full
2.9
2.23
ns
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
Full
2.5
4.8
7.0
2.5
4.8
7.0
ns
DCO Propagation Delay (tDCO)
Full
3.7
5.3
7.3
3.7
5.3
7.3
ns
Pipeline Delay (Latency) NCO, FIR, fS/8 Mix Disabled
Full
38
38
Cycles
Pipeline Delay (Latency) NCO Enabled; FIR and fS/8
Mix Disabled (Complex Output Mode)
Full
38
38
Cycles
Pipeline Delay (Latency) NCO, FIR Filter, and fS/8 Mix
Enabled
Full
109
109
Cycles
Aperture Delay (tA)
Full
1.0
1.0
ns
Aperture Uncertainty (Jitter, tJ)
Full
0.1
0.1
ps rms
Wake-Up Time3
Full
350
350
μs
OUT-OF-RANGE RECOVERY TIME
Full
44
44
Cycles
1 Conversion rate is the clock rate after the divider.
2 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with a 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors.


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