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CDCU877B データシート(PDF) 1 Page - Seme LAB

部品番号 CDCU877B
部品情報  1.8-V PHASE LOCK LOOP CLOCK DRIVER
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FEATURES
DESCRIPTION
CDCU877B
1.8-V PHASE LOCK LOOP CLOCK DRIVER
SCAS801B – JUNE 2005 – REVISED JULY 2007
• Low Dynamic Phase Offset: ±15 ps
• 1.8-V Phase Lock Loop Clock Driver for
• Low Static Phase Offset: ±50 ps
Double Data Rate (DDR II) Applications
• Distributes One Differential Clock Input to Ten
• Spread Spectrum Clock Compatible
Differential Outputs
• Operating Frequency: 10 MHz to 340 MHz
• 52-Ball μBGA (MicroStar™ Junior BGA,
0,65-mm pitch)
• Low Current Consumption: <115 mA
• External Feedback Pins (FBIN, FBIN) are Used
• Low Jitter (Cycle-Cycle): ±30 ps
to Synchronize the Outputs to the Input
• Low Output Skew: 25 ps
Clocks
• Low Period Jitter: ±20 ps
• Fail-Safe Inputs
The CDCU877B is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock
input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.
When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within
the specified stabilization time.
The CDCU877B is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from
—40
°C to 85°C.
ORDERING INFORMATION
TA
52-BALL BGA (1)
-40
°C to 70°C
CDCU877BZQL
(1)
For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see the
TI website at www.ti.com.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MicroStar is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.


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