データシートサーチシステム |
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74AC08 データシート(PDF) 8 Page - Fairchild Semiconductor |
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74AC08 データシート(HTML) 8 Page - Fairchild Semiconductor |
8 / 10 page ©1988 Fairchild Semiconductor Corporation www.fairchildsemi.com 74AC08, 74ACT08 Rev. 1.5.1 8 Physical Dimensions (Continued) Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS F. DRAWING FILE NAME: MTC14REV6 R0.09 min 12.00 °TOP & BOTTOM 0.43 TYP 1.00 D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 R0.09min E. LANDPATTERN STANDARD: SOP65P640X110-14M 0.65 6.10 1.65 0.45 A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS |
同様の部品番号 - 74AC08_08 |
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同様の説明 - 74AC08_08 |
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