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74LV259D データシート(PDF) 9 Page - NXP Semiconductors |
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74LV259D データシート(HTML) 9 Page - NXP Semiconductors |
9 / 19 page 74LV259_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 2 January 2008 9 of 19 NXP Semiconductors 74LV259 8-bit addressable latch 11. Waveforms Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The enable input (LE) to output (Qn) propagation delays and the enable input pulse width 001aah121 LE input Qn output tPHL tPLH tW VM VOH VCC GND VCC GND VOL VM D input Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. The address input (An) to output (Qn) propagation delays 001aah122 An input Qn output tPHL tPLH GND VCC VM VM VOH VOL Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. The data input (D) to output (Qn) propagation delays 001aah123 D input Qn output tPHL tPLH GND VCC VM VM VOH VOL |
同様の部品番号 - 74LV259D |
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同様の説明 - 74LV259D |
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