 |
データシートサーチシステム |
|
|
データシートサーチシステム |
|
ADE8052-PRG1 データシート(PDF) 30 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADE8052-PRG1 データシート(HTML) 30 Page - Analog Devices |
|
|
30 / 144 page  ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 30 of 144 Battery Switchover and Power Supply Restored PSM Interrupt The ADE7566/ADE7569/ADE7166/ADE7169 can be configured to generate a PSM interrupt when the source of VSWOUT changes from VDD to VBAT, indicating battery switchover. Setting the EBSO bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt (see Table 20). The ADE7566/ADE7569/ADE7166/ADE7169 can also be configured to generate an interrupt when the source of VSWOUT changes from VBAT to VDD, indicating that the VDD power supply has been restored. Setting the EPSR bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The flags in the IPSME SFR for these interrupts, FBSO and FPSR, are set regardless of whether the respective enable bits have been set. The battery switchover and power supply restore event flags, FBSO and FPSR, are latched. These events must be cleared by writing a 0 to these bits. Bit 6 in the Peripheral Configuration SFR (PERIPH, 0xF4), VSWSOURCE, tracks the source of VSWOUT. The bit is set when VSWOUT is connected to VDD and cleared when VSWOUT is connected to VBAT. VDCIN ADC PSM Interrupt The ADE7566/ADE7569/ADE7166/ADE7169 can be configured to generate a PSM interrupt when VDCIN changes magnitude by more than a configurable threshold. This threshold is set in the Temperature and Supply Delta SFR (DIFFPROG, 0xF3), which is described in Table 49. See the External Voltage Measurement section for more information. Setting the EVDCIN bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. The VDCIN voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VDCIN. Conversions can also be initiated by writing to the Start ADC Measurement SFR (ADCGO, 0xD8) described in Table 50. The FVDCIN flag indicates when a VDCIN measurement is ready. See the External Voltage Measurement section for details on how VDCIN is measured. VBAT Monitor PSM Interrupt The VBAT voltage is measured using a dedicated ADC. These measurements take place in the background at intervals to check the change in VBAT. The FBAT bit is set when the battery level is lower than the threshold set in the Battery Detection Threshold SFR (BATVTH, 0xFA), described in Table 51, or when a new measurement is ready in the Battery ADC Value SFR (BATADC, 0xDF), described in Table 53. See the Battery Measurement section for more information. Setting the EBAT bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. VDCIN Monitor PSM Interrupt The VDCIN voltage is monitored by a comparator. The FVDCIN bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set when the VDCIN input level is lower than 1.2 V. Setting the EVDCIN bit in the IPSME SFR enables this event to generate a PSM interrupt. This event, which is associated with the SAG monitoring, can be used to detect a power supply (VDD) being compromised and to trigger further actions prior to deciding a switch of VDD to VBAT. SAG Monitor PSM Interrupt The ADE7566/ADE7569/ADE7166/ADE7169 energy measurement DSP monitors the ac voltage input at the VP and VN input pins. The SAGLVL register is used to set the threshold for a line voltage SAG event. The FSAG bit in the Power Management Interrupt Flag SFR (IPSMF, 0xF8) is set if the line voltage stays below the level set in the SAGLVL register for the number of line cycles set in the SAGCYC register. See the Line Voltage SAG Detection section for more information. Setting the ESAG bit in the Power Management Interrupt Enable SFR (IPSME, 0xEC) enables this event to generate a PSM interrupt. |
同様の部品番号 - ADE8052-PRG1 |
|
同様の説明 - ADE8052-PRG1 |
|
|
リンク URL |
| プライバシーポリシー |
| ALLDATASHEET.JP |
| ALLDATASHEETはお客様のビジネスに役立ちますか？ [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Japanese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
