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ADE8052Z-DWDL1 データシート(PDF) 100 Page - Analog Devices |
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ADE8052Z-DWDL1 データシート(HTML) 100 Page - Analog Devices |
100 / 144 page ADE7566/ADE7569/ADE7166/ADE7169 Rev. A | Page 100 of 144 BLINK MODE Blink mode is enabled by setting the BLINKEN bit in the LCD Configuration SFR (LCDCON, 0x95). This mode is used to alternate between the LCD on state and LCD off state so that the LCD screen appears to blink. There are two blinking modes: a software controlled blink mode and an automatic blink mode. Software Controlled Blink Mode The LCD blink rate can be controlled by user code with the BLKMOD[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96) by toggling the bits to turn the display on and off at a rate determined by the MCU code. Automatic Blink Mode There are five blink rates available if the RTC peripheral is enabled by setting the RTCEN bit in the RTC Configuration SFR (TIMECON, 0xA1). These blink rates are selected by the BLKMOD[1:0] and BLKFREQ[1:0] bits in the LCD Clock SFR (LCDCLK, 0x96); see Table 82. DISPLAY ELEMENT CONTROL A bank of 15 bytes of data memory located in the LCD module controls the on or off state of each LCD segment. The LCD data memory is stored in Address 0 through Address 14 in the LCD module. Each byte configures the on and off states of two segment lines. The LSBs store the state of the even numbered segment lines, and the MSBs store the state of the odd numbered segment lines. For example, LCD Data Address 0 refers to segment lines one and zero (see Table 89). Note that the LCD data memory is maintained in PSM2 operating mode. The LCD data memory is accessed indirectly through the LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE). Moving a value to the LCDPTR SFR selects the LCD data byte to be accessed and initiates a read or write operation (see Table 86). Writing to LCD Data Registers To update the LCD data memory, first set the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) to freeze the data being displayed on the LCD while updating it. Then, move the data to the LCD Data SFR (LCDDAT, 0xAE) prior to accessing the LCD Pointer SFR (LCDPTR, 0xAC). When the MSB of the LCDPTR SFR is set, the content of the LCDDAT SFR is transferred to the internal LCD data memory designated by the address in the LCDPTR SFR. Clear the LSB of the LCD Configuration Y SFR (LCDCONY, 0xB1) when all of the data memory has been updated to allow the use of the new LCD setup for display. To update the segments attached to the FP10 and FP11 pins, use the following sample 8052 code: ORL LCDCONY,#01h ;start updating the data MOV LCDDATA,#FFh MOV LCDPTR,#80h OR 05h ANL LCDCONY,#0FEh ;update finished Reading LCD Data Registers When the MSB of the LCD Pointer SFR (LCDPTR, 0xAC) is cleared, the content of the LCD data memory address designated by LCDPTR is transferred to the LCD Data SFR (LCDDAT, 0xAE). Sample 8052 code to read the contents of LCD Data Memory Address 0x07, which holds the on and off state of the segments attached to FP14 and FP15, is as follows. MOV LCDPTR,#07h MOV R1, LCDDATA Table 89. LCD Data Memory Accessed Indirectly Through LCD Pointer SFR (LCDPTR, 0xAC) and LCD Data SFR (LCDDAT, 0xAE)1, 2 LCD Pointer SFR (LCDPTR, 0xAC) LCD Pointer SFR (LCDDAT, 0xAE) LCD Memory Address COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 0x0E FP28 FP28 FP28 FP28 0x0D FP27 FP27 FP27 FP27 FP26 FP26 FP26 FP26 0x0C FP25 FP25 FP25 FP25 FP24 FP24 FP24 FP24 0x0B FP23 FP23 FP23 FP23 FP22 FP22 FP22 FP22 0x0A FP21 FP21 FP21 FP21 FP20 FP20 FP20 FP20 0x09 FP19 FP19 FP19 FP19 FP18 FP18 FP18 FP18 0x08 FP17 FP17 FP17 FP17 FP16 FP16 FP16 FP16 0x07 FP15 FP15 FP15 FP15 FP14 FP14 FP14 FP14 0x06 FP13 FP13 FP13 FP13 FP12 FP12 FP12 FP12 0x05 FP11 FP11 FP11 FP11 FP10 FP10 FP10 FP10 0x04 FP9 FP9 FP9 FP9 FP8 FP8 FP8 FP8 0x03 FP7 FP7 FP7 FP7 FP6 FP6 FP6 FP6 0x02 FP5 FP5 FP5 FP5 FP4 FP4 FP4 FP4 0x01 FP3 FP3 FP3 FP3 FP2 FP2 FP2 FP2 0x00 FP1 FP1 FP1 FP1 FP0 FP0 FP0 FP0 1 COMx designates the common lines. 2 FPx designates the segment lines. |
同様の部品番号 - ADE8052Z-DWDL1 |
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同様の説明 - ADE8052Z-DWDL1 |
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