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SL23EP08ZC-1HT データシート(PDF) 7 Page - SpectraLinear Inc |
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SL23EP08ZC-1HT データシート(HTML) 7 Page - SpectraLinear Inc |
7 / 18 page Rev 1.4, May 28, 2007 Page 7 of 18 SL23EP08 Switching Electrical Characteristics (C-Grade-Cont.) Unless otherwise stated VDD= 3.3V+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C Output Duty Cycle DC3 CL=15pF, Fout=66 MHz, all versions Measured at VDD/2 45 50 55 % Output Duty Cycle DC4 CL=15pF, Fout=133 MHz, all versions Measured at VDD/2 40 50 60 % Output Duty Cycle DC5 CL=15pF, Fout=166 MHz, all versions Measured at VDD/2 45 50 55 % Output Rise/Fall Time tr/f1 CL=30pF, -1, -2 and -4 versions - - 2.2 ns Output Rise/Fall Time tr/f2 CL=15pF, -1, -2 and -4 versions - - 1.5 ns Output Rise/Fall Time tr/f3 CL=30pF, -1H and -2H and versions - - 1.5 ns Output Rise/Fall Time tr/f4 CL=15pF, -1H and -2H and versions - - 1.2 ns Output-to-Output Skew on Same Bank SKW2 -1 and -2, measured from 0.8V to 2.0V, and outputs are equally loaded - 80 150 ps Output-to-Output Skew on Same Bank SKW2 -1H and -2H and -4, measured at VDD/2 and outputs are equally loaded - 70 150 ps Output-to-Output Skew Between Bank A and B SKW3 -1, -1H, 2H and -4, measured at VDD/2 and outputs are equally loaded - 80 150 ps Output-to-Output Skew Between Bank A and B SKW4 -2, measured at VDD/2 and outputs are equally loaded - 130 300 ps Device-to-Device Skew SKW5 All versions, measured at VDD/2 and outputs are equally loaded - 150 400 ps Input-to-Output Delay Dt All versions, CLKIN to FBK rising edge, measured at VDD/2 and outputs are equally loaded and S2=S1=1 -200 - 200 ps Fout=66 MHz and CL=15pF - 75 150 ps Fout=66MHz and CL=30PF - 100 200 ps Cycle-to-Cycle Jitter (-1 and -2 Versions) CCJ1 Fout=166MHz and CL=15pF - 50 100 ps Fout=66 MHz and CL=15pF - 100 200 ps Fout=133MHz and CL=30PF - 150 300 ps Cycle-to-Cycle Jitter (-1H, -2H and -4 Versions) CCJ2 Fout=166MHz and CL=15pF - 75 150 ps PLL Lock Time tLOCK From 0.95VDD and valid clock presented at CLKIN - - 1.0 ms |
同様の部品番号 - SL23EP08ZC-1HT |
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同様の説明 - SL23EP08ZC-1HT |
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