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LM12H458CIVX データシート(PDF) 5 Page - National Semiconductor (TI) |
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LM12H458CIVX データシート(HTML) 5 Page - National Semiconductor (TI) |
5 / 36 page Converter Characteristics (Notes 6, 7, 8, 9) (Continued) The following specifications apply to the LM12454, LM12458, and LM12H458 for V A+=VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12-bit + sign conversion mode, f CLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units DNL 8-Bit + Sign and “Watchdog” Mode Differential Non-Linearity ±3/4 LSB (max) 8-Bit + Sign and “Watchdog” Mode Zero Error After Auto-Zero ±1/2 LSB (max) 8-Bit + Sign and “Watchdog” Full-Scale Error ±1/2 LSB (max) 8-Bit + Sign and “Watchdog” Mode DC Common Mode Error ±1/8 LSB Multiplexer Channel-to-Channel Matching ±0.05 LSB V IN+ Non-Inverting Input Range GND V A+ V (min) V (max) V IN− Inverting Input Range GND V A+ V (min) V (max) V IN+ −VIN− Differential Input Voltage Range −V A + V A+ V (min) V (max) Common Mode Input Voltage Range GND V A+ V (min) V (max) PSS Power Supply Sensitivity (Note 15) Zero Error V A+=VD+=5V ±10% ±0.2 ±1.75 LSB (max) Full-Scale Error V REF+ = 4.5V, VREF− = GND ±0.4 ±2 LSB (max) Linearity Error ±0.2 LSB C REF V REF+/VREF− Input Capacitance 85 pF C IN Selected Multiplexer Channel Input Capacitance 75 pF Converter AC Characteristics (Notes 6, 7, 8, 9) The following specifications apply to the LM12454, LM12458, and LM12H458 for V A+=VD+ = 5V, VREF+ = 5V, VREF− = 0V, 12-bit + sign conversion mode, f CLK = 8.0 MHz (LM12H458) or fCLK = 5.0 MHz (LM12454/8), RS =25 Ω, source impedance for V REF+ and VREF− ≤ 25Ω, fully-differential input with fixed 2.5V common-mode voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C. Symbol Parameter Conditions Typical (Note 10) Limits (Note 11) Units Clock Duty Cycle 50 40 60 % % (min) % (max) t C Conversion Time 13-Bit Resolution, Sequencer State S5 (Figure 15) 44 (t CLK) 44 (t CLK)+50ns (max) 9-Bit Resolution, Sequencer State S5 (Figure 15) 21 (t CLK) 21 (t CLK)+50ns (max) t A Acquisition Time Sequencer State S7 (Figure 15) Built-in minimum for 13-Bits 9(t CLK) 9(t CLK)+50ns (max) Built-in minimum for 9-Bits and “Watchdog” mode 2(t CLK) 2(t CLK)+50ns (max) t Z Auto-Zero Time Sequencer State S2 (Figure 15)76 (t CLK) 76 (t CLK)+50ns (max) t CAL Full Calibration Time Sequencer State S2 (Figure 15) 4944 (t CLK) 4944 (t CLK)+50ns (max) Throughput Rate (Note 18) 89 88 kHz (min) LM12H458 142 140 kHz (min) www.national.com 5 |
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