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LM12458CIV データシート(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部品番号 LM12458CIV
部品情報  12-Bit Sign Data Acquisition System with Self-Calibration
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メーカー  NSC [National Semiconductor (TI)]
ホームページ  http://www.national.com
Logo NSC - National Semiconductor (TI)

LM12458CIV データシート(HTML) 8 Page - National Semiconductor (TI)

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Digital Characteristics (Notes 6, 7)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+=VD+ = 5V, unless otherwise specified.
Boldface limits apply for T
A =TJ =TMIN to TMAX; all other limits TA =TJ = 25˚C.
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
V
IN(1)
Logical “1” Input Voltage
V
A+=VD+ = 5.5V
2.0
V (min)
V
IN(0)
Logical “0” Input Voltage
V
A+=VD+ = 4.5V
0.8
V (max)
I
IN(1)
Logical “1” Input Current
V
IN = 5V
0.005
1.0
µA (max)
I
IN(0)
Logical “0” Input Current
V
IN = 0V
−0.005
−1.0
µA (max)
C
IN
D0–D15 Input Capacitance
6
pF
V
OUT(1)
Logical “1” Output Voltage
V
A+=VD+ = 4.5V
I
OUT = −360 µA
2.4
V (min)
I
OUT = −10 µA
4.25
V (min)
V
OUT(0)
Logical “0” Output Voltage
V
A+=VD+ = 4.5V
I
OUT = 1.6 mA
0.4
V (max)
I
OUT
TRI-STATE® Output Leakage Current
V
OUT = 0V
−0.01
−3.0
µA (max)
V
OUT = 5V
0.01
3.0
µA (max)
Digital Timing Characteristics (Notes 6, 7, 8)
The following specifications apply to the LM12454, LM12458, and LM12H458 for V
A+=VD+ = 5V, tr =tf = 3 ns, and CL = 100
pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for T
A =TJ =TMIN to TMAX; all other
limits T
A =TJ = 25˚C.
Symbol (See Figures
8, 9, 10)
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
Units
1, 3
CS or Address Valid to ALE Low Set-Up
Time
40
ns (min)
2, 4
CS or Address Valid to ALE Low Hold
Time
20
ns (min)
5
ALE Pulse Width
45
ns (min)
6
RD High to Next ALE High
35
ns (min)
7
ALE Low to RD Low
20
ns (min)
8
RD Pulse Width
100
ns (min)
9
RD High to Next RD or WR Low
100
ns (min)
10
ALE Low to WR Low
20
ns (min)
11
WR Pulse Width
60
ns (min)
12
WR High to Next ALE High
75
ns (min)
13
WR High to Next RD or WR Low
140
ns (min)
14
Data Valid to WR High Set-Up Time
40
ns (min)
15
Data Valid to WR High Hold Time
30
ns (min)
16
RD Low to Data Bus Out of TRI-STATE
40
10
ns (min)
70
ns (max)
17
RD High to TRI-STATE
R
L =1k
30
10
ns (min)
110
ns (max)
18
RD Low to Data Valid (Access Time)
30
10
ns (min)
80
ns (max)
20
Address Valid or CS Low to RD Low
20
ns (min)
21
Address Valid or CS Low to WR Low
20
ns (min)
19
Address Invalid from RD or WR High
10
ns (min)
22
INT High from RD Low
30
10
ns (min)
60
ns (max)
23
DMARQ Low from RD Low
30
10
ns (min)
60
ns (max)
www.national.com
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