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MM5483 データシート(PDF) 3 Page - National Semiconductor (TI) |
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MM5483 データシート(HTML) 3 Page - National Semiconductor (TI) |
3 / 7 page Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltage at Any Pin V SS to VSS +10V Operating Temperature −40˚C to +85˚C Storage Temperature −65˚C to +150˚C Power Dissipation 300 mW at +85˚C 350 mW at +25˚C Junction Temperature +150˚C Lead Temperature (Soldering, 10 seconds) 300˚C DC Electrical Characteristics T A within operating range, VDD = 3.0V to 10V, VSS = 0V, unless otherwise specified Parameter Conditions Min Typ Max Units Power Supply 3.0 10 V Average Supply Current, I DD All Outputs Bits = Open, Data Out = Open, BP_Out = Open, Clock In = 0V, Data In = 0V, Data Load = 0V, Osc In = 0V, BP_In = 32Hz V DD = 3.0V 1.5 2.5 µA V DD = 5.0V 10 µA V DD = 10.0V 40 µA Input Voltage Levels Logic “0” Logic “1” Logic “0” Logic “1” Load, Clock, Data V DD = 5.0V V DD = 5.0V V DD = 3.0V V DD = 3.0V 2.4 2.0 0.9 0.4 V V V V Output Current Levels Segments and Data Out Sink Source V DD = 3.0V, VOUT = 0.3V V DD = 3.0V, VOUT = 2.7V 20 20 µA µA BP Out Sink BP Out Source V DD = 3.0V, VOUT = 0.3V V DD = 3.0V, VOUT = 2.7V 320 320 µA µA AC Electrical Characteristics V DD ≥ 4.7V, V SS = 0V unless otherwise specified Symbol Parameter Min Typ Max Units f C Clock Frequency, V DD = 3V 500 kHz t CH Clock Period High (Notes 2, 3) 500 ns t CL Clock Period Low 500 ns t DS Data Set-Up before Clock 300 ns t DH Data Hold Time after Clock 100 ns t LW Minimum Load Pulse Width 500 ns t LTC Load to Clock 400 ns t CDO Clock to Data Valid 400 750 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: AC input waveform specification for test purpose: tr ≤ 20 ns, tf ≤ 20 ns, f = 500 kHz, 50% ± 10% duty cycle. Note 3: Clock input rise and fall times must not excced 300 ms. Note 4: Output offset voltage is ±50 mV with CSEGMENT = 250 pF, CBP = 8750 pF. Functional Description A block diagram for the MM5483 is shown in Figure 1 and a package pinout is shown in Figure 2. Figure 3 shows a possible 3-wire connection system with a typical signal for- mat for Figure 3. Shown in Figure 4, the load input is an asynchronous input and lets data through from the shift register to the output buffers any time it is high. The load input can be connected to V DD for 2-wire control as shown in Figure 5. In the 2-wire control mode, 31 bits (or less depend- ing on the number of segments used) of data are clocked into the MM5483 in a short time frame (with less than 0.1 second there probably will be no noticeable flicker) with no more clocks until new information is to be displayed. If data was slowly clocked in, it can be seen to “walk” across the display in the 2-wire mode. An AC timing diagram can be seen in Figure 6. It should be noted that data out is not a TTL-compatible output. www.national.com 3 |
同様の部品番号 - MM5483_02 |
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同様の説明 - MM5483_02 |
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