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LM56BIMM データシート(PDF) 10 Page - National Semiconductor (TI) |
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LM56BIMM データシート(HTML) 10 Page - National Semiconductor (TI) |
10 / 13 page Application Hints (Continued) 4.0 V REF AND VTEMP CAPACITIVE LOADING The LM56 V REF and VTEMP outputs handle capacitive load- ing well. Without any special precautions, these outputs can drive any capacitive load as shown in Figure 4 . 5.0 NOISY ENVIRONMENTS Over the specified temperature range the LM56 V TEMPout- put has a maximum output impedance of 1500 Ω.Inan extremely noisy environment it may be necessary to add some filtering to minimize noise pickup. It is recommended that 0.1 µF be added from V + to GND to bypass the power supply voltage, as shown in Figure 4 . In a noisy environment it may be necessary to add a capacitor from the V TEMP output to ground. A 1 µF output capacitor with the 1500 Ω output impedance will form a 106 Hz lowpass filter. Since the thermal time constant of the V TEMP output is much slower than the 9.4 ms time constant formed by the RC, the overall response time of the V TEMP output will not be significantly affected. For much larger capacitors this additional time lag will increase the overall response time of the LM56. 6.0 APPLICATIONS CIRCUITS The circuit shown in Figure 5 will reduce the effective bias current error for V T2 as discussed in Section 3.0 to be equivalent to the error term of V T1. For this circuit the effect of the bias current on the first trip point can be defined by the following equations: where I B = 300 nA (the maximum specified error). Similarly, bias current affect on V T2 can be defined by: 01289319 FIGURE 4. Loading of V REF and VTEMP 01289320 FIGURE 5. Reducing Errors Caused by Bias Current www.national.com 10 |
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同様の説明 - LM56BIMM |
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