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L6995D データシート(PDF) 11 Page - STMicroelectronics |
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L6995D データシート(HTML) 11 Page - STMicroelectronics |
11 / 25 page 11/25 L6995 1.6 Protection and fault Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects an overvoltage the OVP pin goes high. To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply has to be removed, and restart with the correct sequence. These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV fault). 1.7 Drivers The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching tran- sition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the volt- age on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage reaches 500mV. This is important since the driver can work properly with a large range of external power MOS- FETS. The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the ex- ternal power MOSFET gate charge and switching frequency. Eq 14 The maximum gate charge values for the low side and high side are given from: Eq 15 Eq 16 Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG can be higher. For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation; in this case the maximum value is QMAXLS = 125nC. The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect. 2 APPLICATION INFORMATION 2.1 20A Demo board description The demoboard shows the device operation in general purpose applications. The evaluation board allows using only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1 is used to start the device (when the supplies are already present) and to select the PFM/PWM mode. P driver V cc Q gTO T F SW ⋅⋅ = Q M AXHS f SW0 f SW ------------- 75 nC ⋅ = Q M AXLS f SW 0 f SW ------------- 125n C ⋅ = |
同様の部品番号 - L6995D |
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同様の説明 - L6995D |
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