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CD54HC40103F データシート(PDF) 2 Page - Texas Instruments |
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CD54HC40103F データシート(HTML) 2 Page - Texas Instruments |
2 / 16 page 2 Pinout CD54HC40103 (CERDIP) CD74HC40103, CD74HCT40103 (PDIP, SOIC) TOP VIEW Functional Diagram TRUTH TABLE CONTROL INPUTS PRESET MODE ACTION MR PL PE TE 1111 Synchronous Inhibit Counter 1110 Count Down 1 1 0 X Preset On Next Positive Clock Transition 1 0 X X Asynchronously Preset Asychronously 0 X X X Clear to Maximum Count 1 = High Level. 0 = Low Level. X = Don’t Care. Clock connected to clock input. Synchronous Operation: changes occur on negative-to-positive clock transitions. Load Inputs: MSB = P7, LSB = P0. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 CP MR TE P0 P1 P2 GND P3 VCC TC P7 P6 P5 P4 PL (ASYNC) PE (SYNC) 7 10 11 12 13 4 5 6 P3 P4 P5 P6 P7 P0 P1 P2 15 9 3 1 2 16 8 14 CD54HC40103, CD74HC40103, CD74HCT40103 |
同様の部品番号 - CD54HC40103F |
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同様の説明 - CD54HC40103F |
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