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74F114 データシート(PDF) 6 Page - NXP Semiconductors

部品番号 74F114
部品情報  Dual J-K negative edge-triggered flip-flop with common clock and reset
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メーカー  PHILIPS [NXP Semiconductors]
ホームページ  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74F114 データシート(HTML) 6 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74F114
Dual J-K negative edge-triggered flip-flop
with common clock and reset
1996 Mar 14
6
TEST CIRCUIT AND WAVEFORMS
tw
90%
VM
10%
90%
VM
10%
90%
VM
10%
90%
VM
10%
NEGATIVE
PULSE
POSITIVE
PULSE
tw
AMP (V)
0V
0V
tTHL (tf )
INPUT PULSE REQUIREMENTS
rep. rate
tw
tTLH
tTHL
1MHz
500ns
2.5ns
2.5ns
Input Pulse Definition
VCC
family
74F
D.U.T.
PULSE
GENERATOR
RL
CL
RT
VIN
VOUT
Test Circuit for Totem-Pole Outputs
DEFINITIONS:
RL = Load resistor;
see AC ELECTRICAL CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC ELECTRICAL CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
tTHL (tf )
tTLH (tr )
tTLH (tr )
AMP (V)
amplitude
3.0V
1.5V
VM
SF00006


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