6.1.3
Power Control ........................................................................................................................... 58
6.1.4
Clock Control ............................................................................................................................ 58
6.1.5
System Control ......................................................................................................................... 60
6.2
Initialization and Configuration ................................................................................................... 61
6.3
Register Map ............................................................................................................................ 61
6.4
Register Descriptions ................................................................................................................ 62
7
Hibernation Module .......................................................................................................... 114
7.1
Block Diagram ........................................................................................................................ 115
7.2
Functional Description ............................................................................................................. 115
7.2.1
Register Access Timing ........................................................................................................... 115
7.2.2
Clock Source .......................................................................................................................... 116
7.2.3
Battery Management ............................................................................................................... 116
7.2.4
Real-Time Clock ...................................................................................................................... 116
7.2.5
Non-Volatile Memory ............................................................................................................... 117
7.2.6
Power Control ......................................................................................................................... 117
7.2.7
Interrupts and Status ............................................................................................................... 117
7.3
Initialization and Configuration ................................................................................................. 118
7.3.1
Initialization ............................................................................................................................. 118
7.3.2
RTC Match Functionality (No Hibernation) ................................................................................ 118
7.3.3
RTC Match/Wake-Up from Hibernation ..................................................................................... 118
7.3.4
External Wake-Up from Hibernation .......................................................................................... 119
7.3.5
RTC/External Wake-Up from Hibernation .................................................................................. 119
7.4
Register Map .......................................................................................................................... 119
7.5
Register Descriptions .............................................................................................................. 120
8
Internal Memory ............................................................................................................... 133
8.1
Block Diagram ........................................................................................................................ 133
8.2
Functional Description ............................................................................................................. 133
8.2.1
SRAM Memory ........................................................................................................................ 133
8.2.2
Flash Memory ......................................................................................................................... 134
8.3
Flash Memory Initialization and Configuration ........................................................................... 135
8.3.1
Flash Programming ................................................................................................................. 135
8.3.2
Nonvolatile Register Programming ........................................................................................... 136
8.4
Register Map .......................................................................................................................... 136
8.5
Flash Register Descriptions (Flash Control Offset) ..................................................................... 137
8.6
Flash Register Descriptions (System Control Offset) .................................................................. 144
9
General-Purpose Input/Outputs (GPIOs) ....................................................................... 157
9.1
Functional Description ............................................................................................................. 157
9.1.1
Data Control ........................................................................................................................... 157
9.1.2
Interrupt Control ...................................................................................................................... 158
9.1.3
Mode Control .......................................................................................................................... 159
9.1.4
Commit Control ....................................................................................................................... 159
9.1.5
Pad Control ............................................................................................................................. 159
9.1.6
Identification ........................................................................................................................... 159
9.2
Initialization and Configuration ................................................................................................. 159
9.3
Register Map .......................................................................................................................... 161
9.4
Register Descriptions .............................................................................................................. 162
September 02, 2007
4
Preliminary
Table of Contents