List of Figures
Figure 1-1.
Stellaris® Fury-class High-Level Block Diagram ................................................................ 28
Figure 2-1.
CPU Block Diagram ......................................................................................................... 36
Figure 2-2.
TPIU Block Diagram ........................................................................................................ 37
Figure 5-1.
JTAG Module Block Diagram ............................................................................................ 47
Figure 5-2.
Test Access Port State Machine ....................................................................................... 50
Figure 5-3.
IDCODE Register Format ................................................................................................. 55
Figure 5-4.
BYPASS Register Format ................................................................................................ 56
Figure 5-5.
Boundary Scan Register Format ....................................................................................... 56
Figure 6-1.
External Circuitry to Extend Reset .................................................................................... 58
Figure 7-1.
Hibernation Module Block Diagram ................................................................................. 116
Figure 8-1.
Flash Block Diagram ...................................................................................................... 133
Figure 9-1.
GPIODATA Write Example ............................................................................................. 158
Figure 9-2.
GPIODATA Read Example ............................................................................................. 158
Figure 10-1.
GPTM Module Block Diagram ........................................................................................ 198
Figure 10-2.
16-Bit Input Edge Count Mode Example .......................................................................... 202
Figure 10-3.
16-Bit Input Edge Time Mode Example ........................................................................... 203
Figure 10-4.
16-Bit PWM Mode Example ............................................................................................ 204
Figure 11-1.
WDT Module Block Diagram .......................................................................................... 230
Figure 12-1.
UART Module Block Diagram ......................................................................................... 254
Figure 12-2.
UART Character Frame ................................................................................................. 255
Figure 12-3.
IrDA Data Modulation ..................................................................................................... 257
Figure 13-1.
SSI Module Block Diagram ............................................................................................. 293
Figure 13-2.
TI Synchronous Serial Frame Format (Single Transfer) .................................................... 296
Figure 13-3.
TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 296
Figure 13-4.
Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 297
Figure 13-5.
Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 297
Figure 13-6.
Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 298
Figure 13-7.
Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 299
Figure 13-8.
Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 299
Figure 13-9.
Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 300
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 301
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 302
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 302
Figure 14-1.
I
2C Block Diagram ......................................................................................................... 328
Figure 14-2.
I
2C Bus Configuration .................................................................................................... 329
Figure 14-3.
START and STOP Conditions ......................................................................................... 329
Figure 14-4.
Complete Data Transfer with a 7-Bit Address ................................................................... 330
Figure 14-5.
R/S Bit in First Byte ........................................................................................................ 330
Figure 14-6.
Data Validity During Bit Transfer on the I
2C Bus ............................................................... 330
Figure 14-7.
Master Single SEND ...................................................................................................... 333
Figure 14-8.
Master Single RECEIVE ................................................................................................. 334
Figure 14-9.
Master Burst SEND ....................................................................................................... 335
Figure 14-10. Master Burst RECEIVE .................................................................................................. 336
Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 337
Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 338
Figure 14-13. Slave Command Sequence ............................................................................................ 339
June 14, 2007
8
Luminary Micro Confidential-Advance Product Information
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