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74F192 データシート(PDF) 2 Page - Fairchild Semiconductor

部品番号 74F192
部品情報  Up/Down Decade Counter with Separate Up/Down Clocks
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メーカー  FAIRCHILD [Fairchild Semiconductor]
ホームページ  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

74F192 データシート(HTML) 2 Page - Fairchild Semiconductor

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Unit Loading/Fan Out
Functional Description
The 74F192 is an asynchronously presettable decade
counter. It contains four edge-triggered flip-flops, with inter-
nal gating and steering logic to provide master reset, indi-
vidual preset, count up and count down operations.
A LOW-to-HIGH transition on the CP input to each flip-flop
causes the output to change state. Synchronous switching,
as opposed to ripple counting, is achieved by driving the
steering gates of all stages from a common Count Up line
and a common Count Down line, thereby causing all state
changes to be initiated simultaneously. A LOW-to-HIGH
transition on the Count Up input will advance the count by
one; a similar transition on the Count Down input will
decrease the count by one. While counting with one clock
input, the other should be held HIGH, as indicated in the
Function Table. Otherwise, the circuit will either count by
twos or not at all, depending on the state of the first flip-
flop, which cannot toggle as long as either clock input is
LOW.
The Terminal Count Up (TCU) and Terminal Count Down
(TCD) outputs are normally HIGH. When the circuit has
reached the maximum count state 9, the next HIGH-to-
LOW transition of the Count Up Clock will cause TCU to go
LOW. TCU will stay LOW until CPU goes HIGH again, thus
effectively repeating the Count Up Clock, but delayed by
two gate delays. Similarly, the TCD output will go LOW
when the circuit is in the zero state and the Count Down
Clock goes LOW. Since the TC outputs repeat the clock
waveforms, they can be used as the clock input signals to
the next higher order circuit in a multistage counter.
TCU = Q0 • Q3 • CPU
TCD = Q0 • Q1 • Q2 • Q3 • CPD
The 74F192 has an asynchronous parallel load capability
permitting the counter to be preset. When the Parallel Load
(PL) and the Master Reset (MR) inputs are LOW, informa-
tion present on the Parallel Data input (P0–P3) is loaded
into the counter and appears on the outputs regardless of
the conditions of the clock inputs. A HIGH signal on the
Master Reset input will disable the preset gates, override
both clock inputs, and latch each Q output in the LOW
state. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of
that clock will be interpreted as a legitimate signal and will
be counted.
Function Table
H
= HIGH Voltage Level
L
= LOW Voltage Level
X
= Immaterial
 = LOW-to-HIGH Clock Transition
State Diagram
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
CPU
Count Up Clock Input (Active Rising Edge)
1.0/3.0
20
µA/−1.8 mA
CPD
Count Down Clock Input (Active Rising Edge)
1.0/3.0
20
µA/−1.8 mA
MR
Asynchronous Master Reset Input (Active HIGH)
1.0/1.0
20
µA/−0.6 mA
PL
Asynchronous Parallel Load Input (Active LOW)
1.0/1.0
20
µA/−0.6 mA
P0–P3
Parallel Data Inputs
1.0/1.0
20
µA/−0.6 mA
Q0–Q3
Flip-Flop Outputs
50/33.3
−1 mA/20 mA
TCD
Terminal Count Down (Borrow) Output (Active LOW)
50/33.3
−1 mA/20 mA
TCU
Terminal Count Up (Carry) Output (Active LOW)
50/33.3
−1 mA/20 mA
MR
PL
CPU
CPD
Mode
H
X
X
X
Reset (Asyn.)
L
L
X
X
Preset (Asyn.)
L
H
H
H
No Change
LH

H
Count Up
LH
H

Count Down


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