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MC141563 データシート(PDF) 5 Page - Motorola, Inc |
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MC141563 データシート(HTML) 5 Page - Motorola, Inc |
5 / 15 page MOTOROLA 3–324 MC141563 AC ELECTRICAL CHARACTERISTICS -WRITE CYCLE (VDD =5.0V, VSS = 0V, VEE = -23V, TA = 25˚C) Symbol Parameter Min Typ Max Unit tSUD Data (D0-D3) to Shift Clock (SCLK) Set up Time 50 - - ns thD Data (D0-D3) to Shift Clock (SCLK) Hold Time 50 - - ns tSULP Data Latch (LP) to Shift Clock (SCLK) Set up Time 50 - - ns thLP Data Latch (LP) to Shift Clock (SCLK) Hold Time 50 - - ns tSUS Enable Input (EIO) to Shift Clock (SCLK) Set up Time 20 - - ns tSUE Shift Clock (SCLK) to Enable Output (EIO) Set up Time 20 - - ns tM tPO tPM tPLP tPE Propagation Delay Time Data Latch (LP) to M Data Latch (LP) to Segment Output (n) CL = 100pF M to Segment Output (n) CL = 100pF Data Latch (LP) to EIO (Output ) CL = 50pF Shift Clock (SCLK) to EIO (Output ) CL = 50pF - - - - - - - - - - 200 0.5 0.5 50 50 ns s s ns ns tTLH tTHL Control Input Rise and Fall Time SCLK, LP, M, EIO1,EIO2 - - 10 10 20 20 ns ns tSCØ Shift Clock (SCLK) Cycle VDD = 3.0V 125 - - ns tSCH Shift Clock (SCLK) Pulse Width HIGH 40 - - ns tSCL Shift Clock (SCLK) Pulse Width LOW 40 - - ns tLPH Data Latch (LP) Pulse Width HIGH 50 - - ns Figure 3. SCLK, LP, Data, M and Segment Output Propagation Delay Timing Diagram |
同様の部品番号 - MC141563 |
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同様の説明 - MC141563 |
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