M54HCT165

M74HCT165

October 1993

8 BIT PISO SHIFT REGISTER

B1R

(Plastic Package)

ORDER CODES :

M54HCT165F1R

M74HCT165M1R

M74HCT165B1R

M74HCT165C1R

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

PIN CONNECTIONS (top view)

NC =

No Internal

Connection

.

HIGH SPEED

.

LOW POWER DISSIPATION

.

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

.

BALANCED PROPAGATION DELAYS

.

SYMMETRICAL OUTPUT IMPEDANCE

.

COMPATIBLE WITH TTL OUTPUTS

.

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS165

DESCRIPTION

The M54/74HCT165 is a high speed CMOS 8 BIT

PISO SHIFT REGISTER fabricated in silicon gate

C

performance of LSTTL combined with true CMOS

low power consumption. It achives the high speed

operation

similar

to

equivalent

LSTTL while

maintaining the CMOS low power dissipation.

This device contains eight clocked master slave RS

flip-flops connected as a shift register, with auxiliary

gating to provide over-riding asynchronous parallel

entry. Parallel data entrens when the shift/load input

is low. The parallel data can change while shift/load

is low, provided that the recommended set-up and

hold times are observed. For clocked operation,

shift/load must be high. The two clock input perform

identically; one can be used as a clock inhibit by

applying a high signal; to permit this operation

clocking is accomplished through a 2 input nor

gates.

To avoid double clocking, however, the inhibit signal

should only go high while the clock is high.

Otherwise the rising inhibit signal will cause the

same response as rising clock edge.This integrated

circuit has input and output characteristics that are

fully compatible with 54/74 LSTTL logic families.

M54/74HCT devices are designed to directly

interface HSCMOS systems with TTL and NMOS

components. They are also plug in replacements for

LSTTL devices giving a reduction of power

consumption.

All

inputs

are

equipped

with

protection circuits against static discharge and

transient excess voltage.

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